source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/no-fpu.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.2 KB
Line 
1; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,-vfp2 | FileCheck --check-prefix=NONEON-NOVFP %s
2; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon | FileCheck --check-prefix=NONEON %s
3; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-vfp2 | FileCheck --check-prefix=NOVFP %s
4; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,+vfp2 | FileCheck --check-prefix=NONEON-VFP %s
5
6; Check no NEON instructions are selected when feature is disabled.
7define void @neonop(i64* nocapture readonly %a, i64* nocapture %b) #0 {
8  %1 = bitcast i64* %a to <2 x i64>*
9  %wide.load = load <2 x i64>, <2 x i64>* %1, align 8
10  ; NONEON-NOVFP-NOT: vld1.64
11  ; NONEON-NOT: vld1.64
12  %add = add <2 x i64> %wide.load, %wide.load
13  ; NONEON-NOVFP-NOT: vadd.i64
14  ; NONEON-NOT: vadd.i64
15  %2 = bitcast i64* %b to <2 x i64>*
16  store <2 x i64> %add, <2 x i64>* %2, align 8
17  ; NONEON-NOVFP-NOT: vst1.64
18  ; NONEON-NOT: vst1.64
19  ret void
20}
21
22; Likewise with VFP instructions.
23define double @fpmult(double %a, double %b) {
24  %res = fmul double %a, %b
25  ; NONEON-NOVFP-NOT: vmov
26  ; NONEON-NOVFP-NOT: vmul.f64
27  ; NOVFP-NOT: vmov
28  ; NOVFP-NOT: vmul.f64
29  ; NONEON-VFP: vmov
30  ; NONEON-VFP: vmul.f64
31  ret double %res
32}
33
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