source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/rev.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 2.9 KB
Line 
1; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
2
3define i32 @test1(i32 %X) nounwind {
4; CHECK: test1
5; CHECK: rev16 r0, r0
6        %tmp1 = lshr i32 %X, 8
7        %X15 = bitcast i32 %X to i32
8        %tmp4 = shl i32 %X15, 8
9        %tmp2 = and i32 %tmp1, 16711680
10        %tmp5 = and i32 %tmp4, -16777216
11        %tmp9 = and i32 %tmp1, 255
12        %tmp13 = and i32 %tmp4, 65280
13        %tmp6 = or i32 %tmp5, %tmp2
14        %tmp10 = or i32 %tmp6, %tmp13
15        %tmp14 = or i32 %tmp10, %tmp9
16        ret i32 %tmp14
17}
18
19define i32 @test2(i32 %X) nounwind {
20; CHECK: test2
21; CHECK: revsh r0, r0
22        %tmp1 = lshr i32 %X, 8
23        %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
24        %tmp3 = trunc i32 %X to i16
25        %tmp2 = and i16 %tmp1.upgrd.1, 255
26        %tmp4 = shl i16 %tmp3, 8
27        %tmp5 = or i16 %tmp2, %tmp4
28        %tmp5.upgrd.2 = sext i16 %tmp5 to i32
29        ret i32 %tmp5.upgrd.2
30}
31
32; rdar://9147637
33define i32 @test3(i16 zeroext %a) nounwind {
34entry:
35; CHECK-LABEL: test3:
36; CHECK: revsh r0, r0
37  %0 = tail call i16 @llvm.bswap.i16(i16 %a)
38  %1 = sext i16 %0 to i32
39  ret i32 %1
40}
41
42declare i16 @llvm.bswap.i16(i16) nounwind readnone
43
44define i32 @test4(i16 zeroext %a) nounwind {
45entry:
46; CHECK-LABEL: test4:
47; CHECK: revsh r0, r0
48  %conv = zext i16 %a to i32
49  %shr9 = lshr i16 %a, 8
50  %conv2 = zext i16 %shr9 to i32
51  %shl = shl nuw nsw i32 %conv, 8
52  %or = or i32 %conv2, %shl
53  %sext = shl i32 %or, 16
54  %conv8 = ashr exact i32 %sext, 16
55  ret i32 %conv8
56}
57
58; rdar://9609059
59define i32 @test5(i32 %i) nounwind readnone {
60entry:
61; CHECK: test5
62; CHECK: revsh r0, r0
63  %shl = shl i32 %i, 24
64  %shr = ashr exact i32 %shl, 16
65  %shr23 = lshr i32 %i, 8
66  %and = and i32 %shr23, 255
67  %or = or i32 %shr, %and
68  ret i32 %or
69}
70
71; rdar://9609108
72define i32 @test6(i32 %x) nounwind readnone {
73entry:
74; CHECK: test6
75; CHECK: rev16 r0, r0
76  %and = shl i32 %x, 8
77  %shl = and i32 %and, 65280
78  %and2 = lshr i32 %x, 8
79  %shr11 = and i32 %and2, 255
80  %shr5 = and i32 %and2, 16711680
81  %shl9 = and i32 %and, -16777216
82  %or = or i32 %shr5, %shl9
83  %or6 = or i32 %or, %shr11
84  %or10 = or i32 %or6, %shl
85  ret i32 %or10
86}
87
88; rdar://9164521
89define i32 @test7(i32 %a) nounwind readnone {
90entry:
91; CHECK: test7
92; CHECK: rev r0, r0
93; CHECK: lsr r0, r0, #16
94  %and = lshr i32 %a, 8
95  %shr3 = and i32 %and, 255
96  %and2 = shl i32 %a, 8
97  %shl = and i32 %and2, 65280
98  %or = or i32 %shr3, %shl
99  ret i32 %or
100}
101
102define i32 @test8(i32 %a) nounwind readnone {
103entry:
104; CHECK: test8
105; CHECK: revsh r0, r0
106  %and = lshr i32 %a, 8
107  %shr4 = and i32 %and, 255
108  %and2 = shl i32 %a, 8
109  %or = or i32 %shr4, %and2
110  %sext = shl i32 %or, 16
111  %conv3 = ashr exact i32 %sext, 16
112  ret i32 %conv3
113}
114
115; rdar://10750814
116define zeroext i16 @test9(i16 zeroext %v) nounwind readnone {
117entry:
118; CHECK: test9
119; CHECK: rev16 r0, r0
120  %conv = zext i16 %v to i32
121  %shr4 = lshr i32 %conv, 8
122  %shl = shl nuw nsw i32 %conv, 8
123  %or = or i32 %shr4, %shl
124  %conv3 = trunc i32 %or to i16
125  ret i16 %conv3
126}
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