source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/special-reg-acore.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 2.4 KB
Line 
1; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE
2; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE
3
4; MCORE: LLVM ERROR: Invalid register name "cpsr".
5
6define i32 @read_cpsr() nounwind {
7  ; ACORE-LABEL: read_cpsr:
8  ; ACORE: mrs r0, apsr
9  %reg = call i32 @llvm.read_register.i32(metadata !1)
10  ret i32 %reg
11}
12
13define i32 @read_aclass_registers() nounwind {
14entry:
15  ; ACORE-LABEL: read_aclass_registers:
16  ; ACORE: mrs r0, apsr
17  ; ACORE: mrs r1, spsr
18
19  %0 = call i32 @llvm.read_register.i32(metadata !0)
20  %1 = call i32 @llvm.read_register.i32(metadata !1)
21  %add1 = add i32 %1, %0
22  %2 = call i32 @llvm.read_register.i32(metadata !2)
23  %add2 = add i32 %add1, %2
24  ret i32 %add2
25}
26
27define void @write_aclass_registers(i32 %x) nounwind {
28entry:
29  ; ACORE-LABEL: write_aclass_registers:
30  ; ACORE:   msr APSR_nzcvq, r0
31  ; ACORE:   msr APSR_g, r0
32  ; ACORE:   msr APSR_nzcvqg, r0
33  ; ACORE:   msr CPSR_c, r0
34  ; ACORE:   msr CPSR_x, r0
35  ; ACORE:   msr APSR_g, r0
36  ; ACORE:   msr APSR_nzcvq, r0
37  ; ACORE:   msr CPSR_fsxc, r0
38  ; ACORE:   msr SPSR_c, r0
39  ; ACORE:   msr SPSR_x, r0
40  ; ACORE:   msr SPSR_s, r0
41  ; ACORE:   msr SPSR_f, r0
42  ; ACORE:   msr SPSR_fsxc, r0
43
44  call void @llvm.write_register.i32(metadata !3, i32 %x)
45  call void @llvm.write_register.i32(metadata !4, i32 %x)
46  call void @llvm.write_register.i32(metadata !5, i32 %x)
47  call void @llvm.write_register.i32(metadata !6, i32 %x)
48  call void @llvm.write_register.i32(metadata !7, i32 %x)
49  call void @llvm.write_register.i32(metadata !8, i32 %x)
50  call void @llvm.write_register.i32(metadata !9, i32 %x)
51  call void @llvm.write_register.i32(metadata !10, i32 %x)
52  call void @llvm.write_register.i32(metadata !11, i32 %x)
53  call void @llvm.write_register.i32(metadata !12, i32 %x)
54  call void @llvm.write_register.i32(metadata !13, i32 %x)
55  call void @llvm.write_register.i32(metadata !14, i32 %x)
56  call void @llvm.write_register.i32(metadata !15, i32 %x)
57  ret void
58}
59
60declare i32 @llvm.read_register.i32(metadata) nounwind
61declare void @llvm.write_register.i32(metadata, i32) nounwind
62
63!0 = !{!"apsr"}
64!1 = !{!"cpsr"}
65!2 = !{!"spsr"}
66!3 = !{!"apsr_nzcvq"}
67!4 = !{!"apsr_g"}
68!5 = !{!"apsr_nzcvqg"}
69!6 = !{!"cpsr_c"}
70!7 = !{!"cpsr_x"}
71!8 = !{!"cpsr_s"}
72!9 = !{!"cpsr_f"}
73!10 = !{!"cpsr_cxsf"}
74!11 = !{!"spsr_c"}
75!12 = !{!"spsr_x"}
76!13 = !{!"spsr_s"}
77!14 = !{!"spsr_f"}
78!15 = !{!"spsr_cxsf"}
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