source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/CPP/atomic.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 4.3 KB
Line 
1; RUN: llc -march=cpp -o - %s | FileCheck %s
2
3define void @test_atomicrmw(i32* %addr, i32 %inc) {
4  %inst0 = atomicrmw xchg i32* %addr, i32 %inc seq_cst
5  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThread
6  ; CHECK: [[INST]]->setName("inst0");
7  ; CHECK: [[INST]]->setVolatile(false);
8
9  %inst1 = atomicrmw add i32* %addr, i32 %inc seq_cst
10  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThread
11  ; CHECK: [[INST]]->setName("inst1");
12  ; CHECK: [[INST]]->setVolatile(false);
13
14  %inst2 = atomicrmw volatile sub i32* %addr, i32 %inc singlethread monotonic
15  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Monotonic, SingleThread
16  ; CHECK: [[INST]]->setName("inst2");
17  ; CHECK: [[INST]]->setVolatile(true);
18
19  %inst3 = atomicrmw and i32* %addr, i32 %inc acq_rel
20  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, AcquireRelease, CrossThread
21  ; CHECK: [[INST]]->setName("inst3");
22  ; CHECK: [[INST]]->setVolatile(false);
23
24  %inst4 = atomicrmw nand i32* %addr, i32 %inc release
25  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.*}}, Release, CrossThread
26  ; CHECK: [[INST]]->setName("inst4");
27  ; CHECK: [[INST]]->setVolatile(false);
28
29  %inst5 = atomicrmw volatile or i32* %addr, i32 %inc singlethread seq_cst
30  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThread
31  ; CHECK: [[INST]]->setName("inst5");
32  ; CHECK: [[INST]]->setVolatile(true);
33
34  %inst6 = atomicrmw xor i32* %addr, i32 %inc release
35  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.*}}, Release, CrossThread
36  ; CHECK: [[INST]]->setName("inst6");
37  ; CHECK: [[INST]]->setVolatile(false);
38
39  %inst7 = atomicrmw volatile max i32* %addr, i32 %inc singlethread monotonic
40  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.*}}, Monotonic, SingleThread
41  ; CHECK: [[INST]]->setName("inst7");
42  ; CHECK: [[INST]]->setVolatile(true);
43
44  %inst8 = atomicrmw min i32* %addr, i32 %inc acquire
45  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.*}}, Acquire, CrossThread
46  ; CHECK: [[INST]]->setName("inst8");
47  ; CHECK: [[INST]]->setVolatile(false);
48
49  %inst9 = atomicrmw volatile umax i32* %addr, i32 %inc monotonic
50  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Monotonic, CrossThread
51  ; CHECK: [[INST]]->setName("inst9");
52  ; CHECK: [[INST]]->setVolatile(true);
53
54  %inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release
55  ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread
56  ; CHECK: [[INST]]->setName("inst10");
57  ; CHECK: [[INST]]->setVolatile(false);
58
59
60  ret void
61}
62
63define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
64  %inst0 = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
65  ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
66  ; CHECK: [[INST]]->setName("inst0");
67  ; CHECK: [[INST]]->setVolatile(false);
68  ; CHECK: [[INST]]->setWeak(false);
69
70  %inst1 = cmpxchg volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
71  ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
72  ; CHECK: [[INST]]->setName("inst1");
73  ; CHECK: [[INST]]->setVolatile(true);
74  ; CHECK: [[INST]]->setWeak(false);
75
76  %inst2 = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
77  ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread
78  ; CHECK: [[INST]]->setName("inst2");
79  ; CHECK: [[INST]]->setVolatile(false);
80  ; CHECK: [[INST]]->setWeak(true);
81
82  %inst3 = cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire
83  ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread
84  ; CHECK: [[INST]]->setName("inst3");
85  ; CHECK: [[INST]]->setVolatile(true);
86  ; CHECK: [[INST]]->setWeak(true);
87
88  ret void
89}
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