source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/Hexagon/clr_set_toggle.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 4.2 KB
Line 
1; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s
2; Optimized bitwise operations.
3
4define i32 @my_clrbit(i32 %x) nounwind {
5entry:
6; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
7  %x.addr = alloca i32, align 4
8  store i32 %x, i32* %x.addr, align 4
9  %0 = load i32, i32* %x.addr, align 4
10  %and = and i32 %0, 2147483647
11  ret i32 %and
12}
13
14define i64 @my_clrbit2(i64 %x) nounwind {
15entry:
16; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
17  %x.addr = alloca i64, align 8
18  store i64 %x, i64* %x.addr, align 8
19  %0 = load i64, i64* %x.addr, align 8
20  %and = and i64 %0, -2147483649
21  ret i64 %and
22}
23
24define i64 @my_clrbit3(i64 %x) nounwind {
25entry:
26; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
27  %x.addr = alloca i64, align 8
28  store i64 %x, i64* %x.addr, align 8
29  %0 = load i64, i64* %x.addr, align 8
30  %and = and i64 %0, 9223372036854775807
31  ret i64 %and
32}
33
34define i32 @my_clrbit4(i32 %x) nounwind {
35entry:
36; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
37  %x.addr = alloca i32, align 4
38  store i32 %x, i32* %x.addr, align 4
39  %0 = load i32, i32* %x.addr, align 4
40  %and = and i32 %0, -8193
41  ret i32 %and
42}
43
44define i64 @my_clrbit5(i64 %x) nounwind {
45entry:
46; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
47  %x.addr = alloca i64, align 8
48  store i64 %x, i64* %x.addr, align 8
49  %0 = load i64, i64* %x.addr, align 8
50  %and = and i64 %0, -8193
51  ret i64 %and
52}
53
54define i64 @my_clrbit6(i64 %x) nounwind {
55entry:
56; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27)
57  %x.addr = alloca i64, align 8
58  store i64 %x, i64* %x.addr, align 8
59  %0 = load i64, i64* %x.addr, align 8
60  %and = and i64 %0, -576460752303423489
61  ret i64 %and
62}
63
64define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
65entry:
66; CHECK: memh(r{{[0-9]+}}+#0){{ *}}={{ *}}setbit(#15)
67  %crc.addr = alloca i16, align 2
68  store i16 %crc, i16* %crc.addr, align 2
69  %0 = load i16, i16* %crc.addr, align 2
70  %conv = zext i16 %0 to i32
71  %or = or i32 %conv, 32768
72  %conv1 = trunc i32 %or to i16
73  store i16 %conv1, i16* %crc.addr, align 2
74  %1 = load i16, i16* %crc.addr, align 2
75  ret i16 %1
76}
77
78define i32 @my_setbit2(i32 %x) nounwind {
79entry:
80; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
81  %x.addr = alloca i32, align 4
82  store i32 %x, i32* %x.addr, align 4
83  %0 = load i32, i32* %x.addr, align 4
84  %or = or i32 %0, 32768
85  ret i32 %or
86}
87
88define i64 @my_setbit3(i64 %x) nounwind {
89entry:
90; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
91  %x.addr = alloca i64, align 8
92  store i64 %x, i64* %x.addr, align 8
93  %0 = load i64, i64* %x.addr, align 8
94  %or = or i64 %0, 32768
95  ret i64 %or
96}
97
98define i32 @my_setbit4(i32 %x) nounwind {
99entry:
100; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31)
101  %x.addr = alloca i32, align 4
102  store i32 %x, i32* %x.addr, align 4
103  %0 = load i32, i32* %x.addr, align 4
104  %or = or i32 %0, -2147483648
105  ret i32 %or
106}
107
108define i64 @my_setbit5(i64 %x) nounwind {
109entry:
110; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13)
111  %x.addr = alloca i64, align 8
112  store i64 %x, i64* %x.addr, align 8
113  %0 = load i64, i64* %x.addr, align 8
114  %or = or i64 %0, 35184372088832
115  ret i64 %or
116}
117
118define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
119entry:
120; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
121  %crc.addr = alloca i16, align 2
122  store i16 %crc, i16* %crc.addr, align 2
123  %0 = load i16, i16* %crc.addr, align 2
124  %conv = zext i16 %0 to i32
125  %xor = xor i32 %conv, 32768
126  %conv1 = trunc i32 %xor to i16
127  store i16 %conv1, i16* %crc.addr, align 2
128  %1 = load i16, i16* %crc.addr, align 2
129  ret i16 %1
130}
131
132define i32 @my_togglebit2(i32 %x) nounwind {
133entry:
134; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
135  %x.addr = alloca i32, align 4
136  store i32 %x, i32* %x.addr, align 4
137  %0 = load i32, i32* %x.addr, align 4
138  %xor = xor i32 %0, 32768
139  ret i32 %xor
140}
141
142define i64 @my_togglebit3(i64 %x) nounwind {
143entry:
144; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
145  %x.addr = alloca i64, align 8
146  store i64 %x, i64* %x.addr, align 8
147  %0 = load i64, i64* %x.addr, align 8
148  %xor = xor i64 %0, 32768
149  ret i64 %xor
150}
151
152define i64 @my_togglebit4(i64 %x) nounwind {
153entry:
154; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20)
155  %x.addr = alloca i64, align 8
156  store i64 %x, i64* %x.addr, align 8
157  %0 = load i64, i64* %x.addr, align 8
158  %xor = xor i64 %0, 4503599627370496
159  ret i64 %xor
160}
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