source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
2; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \
3; RUN: FileCheck -check-prefix=CHECK-CALL %s
4; Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU
5
6; CHECK-CALL-NOT: call
7
8; Absolute value doubleword
9declare i64 @llvm.hexagon.A2.absp(i64)
10define i64 @A2_absp(i64 %a) {
11  %z = call i64 @llvm.hexagon.A2.absp(i64 %a)
12  ret i64 %z
13}
14; CHECK: = abs({{.*}})
15
16; Absolute value word
17declare i32 @llvm.hexagon.A2.abs(i32)
18define i32 @A2_abs(i32 %a) {
19  %z = call i32 @llvm.hexagon.A2.abs(i32 %a)
20  ret i32 %z
21}
22; CHECK: = abs({{.*}})
23
24declare i32 @llvm.hexagon.A2.abssat(i32)
25define i32 @A2_abssat(i32 %a) {
26  %z = call i32 @llvm.hexagon.A2.abssat(i32 %a)
27  ret i32 %z
28}
29; CHECK: = abs({{.*}}):sat
30
31; Add and accumulate
32declare i32 @llvm.hexagon.S4.addaddi(i32, i32, i32)
33define i32 @S4_addaddi(i32 %a, i32 %b) {
34  %z = call i32 @llvm.hexagon.S4.addaddi(i32 %a, i32 %b, i32 0)
35  ret i32 %z
36}
37; CHECK: = add({{.*}}, add({{.*}}, #0))
38
39declare i32 @llvm.hexagon.S4.subaddi(i32, i32, i32)
40define i32 @S4_subaddi(i32 %a, i32 %b) {
41  %z = call i32 @llvm.hexagon.S4.subaddi(i32 %a, i32 0, i32 %b)
42  ret i32 %z
43}
44; CHECK: = add({{.*}}, sub(#0, {{.*}}))
45
46declare i32 @llvm.hexagon.M2.accii(i32, i32, i32)
47define i32 @M2_accii(i32 %a, i32 %b) {
48  %z = call i32 @llvm.hexagon.M2.accii(i32 %a, i32 %b, i32 0)
49  ret i32 %z
50}
51; CHECK: += add({{.*}}, #0)
52
53declare i32 @llvm.hexagon.M2.naccii(i32, i32, i32)
54define i32 @M2_naccii(i32 %a, i32 %b) {
55  %z = call i32 @llvm.hexagon.M2.naccii(i32 %a, i32 %b, i32 0)
56  ret i32 %z
57}
58; CHECK: -= add({{.*}}, #0)
59
60declare i32 @llvm.hexagon.M2.acci(i32, i32, i32)
61define i32 @M2_acci(i32 %a, i32 %b, i32 %c) {
62  %z = call i32 @llvm.hexagon.M2.acci(i32 %a, i32 %b, i32 %c)
63  ret i32 %z
64}
65; CHECK: += add({{.*}}, {{.*}})
66
67declare i32 @llvm.hexagon.M2.nacci(i32, i32, i32)
68define i32 @M2_nacci(i32 %a, i32 %b, i32 %c) {
69  %z = call i32 @llvm.hexagon.M2.nacci(i32 %a, i32 %b, i32 %c)
70  ret i32 %z
71}
72; CHECK: -= add({{.*}}, {{.*}})
73
74; Add doublewords
75declare i64 @llvm.hexagon.A2.addp(i64, i64)
76define i64 @A2_addp(i64 %a, i64 %b) {
77  %z = call i64 @llvm.hexagon.A2.addp(i64 %a, i64 %b)
78  ret i64 %z
79}
80; CHECK: = add({{.*}}, {{.*}})
81
82declare i64 @llvm.hexagon.A2.addpsat(i64, i64)
83define i64 @A2_addpsat(i64 %a, i64 %b) {
84  %z = call i64 @llvm.hexagon.A2.addpsat(i64 %a, i64 %b)
85  ret i64 %z
86}
87; CHECK: = add({{.*}}, {{.*}}):sat
88
89; Add halfword
90declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32)
91define i32 @A2_addh_l16_ll(i32 %a, i32 %b) {
92  %z = call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %a, i32 %b)
93  ret i32 %z
94}
95; CHECK: = add({{.*}}.l, {{.*}}.l)
96
97declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32)
98define i32 @A2_addh_l16_hl(i32 %a, i32 %b) {
99  %z = call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %a, i32 %b)
100  ret i32 %z
101}
102; CHECK: = add({{.*}}.l, {{.*}}.h)
103
104declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32)
105define i32 @A2_addh_l16_sat.ll(i32 %a, i32 %b) {
106  %z = call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %a, i32 %b)
107  ret i32 %z
108}
109; CHECK: = add({{.*}}.l, {{.*}}.l):sat
110
111declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32)
112define i32 @A2_addh_l16_sat.hl(i32 %a, i32 %b) {
113  %z = call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %a, i32 %b)
114  ret i32 %z
115}
116; CHECK: = add({{.*}}.l, {{.*}}.h):sat
117
118declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32)
119define i32 @A2_addh_h16_ll(i32 %a, i32 %b) {
120  %z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b)
121  ret i32 %z
122}
123; CHECK: = add({{.*}}.l, {{.*}}.l):<<16
124
125declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32)
126define i32 @A2_addh_h16_lh(i32 %a, i32 %b) {
127  %z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b)
128  ret i32 %z
129}
130; CHECK: = add({{.*}}.l, {{.*}}.h):<<16
131
132declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32)
133define i32 @A2_addh_h16_hl(i32 %a, i32 %b) {
134  %z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b)
135  ret i32 %z
136}
137; CHECK: = add({{.*}}.h, {{.*}}.l):<<16
138
139declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32)
140define i32 @A2_addh_h16_hh(i32 %a, i32 %b) {
141  %z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b)
142  ret i32 %z
143}
144; CHECK: = add({{.*}}.h, {{.*}}.h):<<16
145
146declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
147define i32 @A2_addh_h16_sat_ll(i32 %a, i32 %b) {
148  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
149  ret i32 %z
150}
151; CHECK: = add({{.*}}.l, {{.*}}.l):sat:<<16
152
153declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32)
154define i32 @A2_addh_h16_sat_lh(i32 %a, i32 %b) {
155  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %a, i32 %b)
156  ret i32 %z
157}
158; CHECK: = add({{.*}}.l, {{.*}}.h):sat:<<16
159
160declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32)
161define i32 @A2_addh_h16_sat_hl(i32 %a, i32 %b) {
162  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %a, i32 %b)
163  ret i32 %z
164}
165; CHECK: = add({{.*}}.h, {{.*}}.l):sat:<<16
166
167declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32)
168define i32 @A2_addh_h16_sat_hh(i32 %a, i32 %b) {
169  %z = call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %a, i32 %b)
170  ret i32 %z
171}
172; CHECK: = add({{.*}}.h, {{.*}}.h):sat:<<16
173
174; Logical doublewords
175declare i64 @llvm.hexagon.A2.notp(i64)
176define i64 @A2_notp(i64 %a) {
177  %z = call i64 @llvm.hexagon.A2.notp(i64 %a)
178  ret i64 %z
179}
180; CHECK: = not({{.*}})
181
182declare i64 @llvm.hexagon.A2.andp(i64, i64)
183define i64 @A2_andp(i64 %a, i64 %b) {
184  %z = call i64 @llvm.hexagon.A2.andp(i64 %a, i64 %b)
185  ret i64 %z
186}
187; CHECK: = and({{.*}}, {{.*}})
188
189declare i64 @llvm.hexagon.A4.andnp(i64, i64)
190define i64 @A2_andnp(i64 %a, i64 %b) {
191  %z = call i64 @llvm.hexagon.A4.andnp(i64 %a, i64 %b)
192  ret i64 %z
193}
194; CHECK: = and({{.*}}, ~{{.*}})
195
196declare i64 @llvm.hexagon.A2.orp(i64, i64)
197define i64 @A2_orp(i64 %a, i64 %b) {
198  %z = call i64 @llvm.hexagon.A2.orp(i64 %a, i64 %b)
199  ret i64 %z
200}
201; CHECK: = or({{.*}}, {{.*}})
202
203declare i64 @llvm.hexagon.A4.ornp(i64, i64)
204define i64 @A2_ornp(i64 %a, i64 %b) {
205  %z = call i64 @llvm.hexagon.A4.ornp(i64 %a, i64 %b)
206  ret i64 %z
207}
208; CHECK: = or({{.*}}, ~{{.*}})
209
210declare i64 @llvm.hexagon.A2.xorp(i64, i64)
211define i64 @A2_xorp(i64 %a, i64 %b) {
212  %z = call i64 @llvm.hexagon.A2.xorp(i64 %a, i64 %b)
213  ret i64 %z
214}
215; CHECK: = xor({{.*}}, {{.*}})
216
217; Logical-logical doublewords
218declare i64 @llvm.hexagon.M4.xor.xacc(i64, i64, i64)
219define i64 @M4_xor_xacc(i64 %a, i64 %b, i64 %c) {
220  %z = call i64 @llvm.hexagon.M4.xor.xacc(i64 %a, i64 %b, i64 %c)
221  ret i64 %z
222}
223; CHECK: ^= xor({{.*}}, {{.*}})
224
225; Logical-logical words
226declare i32 @llvm.hexagon.S4.or.andi(i32, i32, i32)
227define i32 @S4_or_andi(i32 %a, i32 %b) {
228  %z = call i32 @llvm.hexagon.S4.or.andi(i32 %a, i32 %b, i32 0)
229  ret i32 %z
230}
231; CHECK: |= and({{.*}}, #0)
232
233declare i32 @llvm.hexagon.S4.or.andix(i32, i32, i32)
234define i32 @S4_or_andix(i32 %a, i32 %b) {
235  %z = call i32 @llvm.hexagon.S4.or.andix(i32 %a, i32 %b, i32 0)
236  ret i32 %z
237}
238; CHECK: = or({{.*}}, and({{.*}}, #0))
239
240declare i32 @llvm.hexagon.M4.or.andn(i32, i32, i32)
241define i32 @M4_or_andn(i32 %a, i32 %b, i32 %c) {
242  %z = call i32 @llvm.hexagon.M4.or.andn(i32 %a, i32 %b, i32 %c)
243  ret i32 %z
244}
245; CHECK: |= and({{.*}}, ~{{.*}})
246
247declare i32 @llvm.hexagon.M4.and.andn(i32, i32, i32)
248define i32 @M4_and_andn(i32 %a, i32 %b, i32 %c) {
249  %z = call i32 @llvm.hexagon.M4.and.andn(i32 %a, i32 %b, i32 %c)
250  ret i32 %z
251}
252; CHECK: &= and({{.*}}, ~{{.*}})
253
254declare i32 @llvm.hexagon.M4.xor.andn(i32, i32, i32)
255define i32 @M4_xor_andn(i32 %a, i32 %b, i32 %c) {
256  %z = call i32 @llvm.hexagon.M4.xor.andn(i32 %a, i32 %b, i32 %c)
257  ret i32 %z
258}
259; CHECK: ^= and({{.*}}, ~{{.*}})
260
261declare i32 @llvm.hexagon.M4.and.and(i32, i32, i32)
262define i32 @M4_and_and(i32 %a, i32 %b, i32 %c) {
263  %z = call i32 @llvm.hexagon.M4.and.and(i32 %a, i32 %b, i32 %c)
264  ret i32 %z
265}
266; CHECK: &= and({{.*}}, {{.*}})
267
268declare i32 @llvm.hexagon.M4.and.or(i32, i32, i32)
269define i32 @M4_and_or(i32 %a, i32 %b, i32 %c) {
270  %z = call i32 @llvm.hexagon.M4.and.or(i32 %a, i32 %b, i32 %c)
271  ret i32 %z
272}
273; CHECK: &= or({{.*}}, {{.*}})
274
275declare i32 @llvm.hexagon.M4.and.xor(i32, i32, i32)
276define i32 @M4_and_xor(i32 %a, i32 %b, i32 %c) {
277  %z = call i32 @llvm.hexagon.M4.and.xor(i32 %a, i32 %b, i32 %c)
278  ret i32 %z
279}
280; CHECK: &= xor({{.*}}, {{.*}})
281
282declare i32 @llvm.hexagon.M4.or.and(i32, i32, i32)
283define i32 @M4_or_and(i32 %a, i32 %b, i32 %c) {
284  %z = call i32 @llvm.hexagon.M4.or.and(i32 %a, i32 %b, i32 %c)
285  ret i32 %z
286}
287; CHECK: |= and({{.*}}, {{.*}})
288
289declare i32 @llvm.hexagon.M4.or.or(i32, i32, i32)
290define i32 @M4_or_or(i32 %a, i32 %b, i32 %c) {
291  %z = call i32 @llvm.hexagon.M4.or.or(i32 %a, i32 %b, i32 %c)
292  ret i32 %z
293}
294; CHECK: |= or({{.*}}, {{.*}})
295
296declare i32 @llvm.hexagon.M4.or.xor(i32, i32, i32)
297define i32 @M4_or_xor(i32 %a, i32 %b, i32 %c) {
298  %z = call i32 @llvm.hexagon.M4.or.xor(i32 %a, i32 %b, i32 %c)
299  ret i32 %z
300}
301; CHECK: |= xor({{.*}}, {{.*}})
302
303declare i32 @llvm.hexagon.M4.xor.and(i32, i32, i32)
304define i32 @M4_xor_and(i32 %a, i32 %b, i32 %c) {
305  %z = call i32 @llvm.hexagon.M4.xor.and(i32 %a, i32 %b, i32 %c)
306  ret i32 %z
307}
308; CHECK: ^= and({{.*}}, {{.*}})
309
310declare i32 @llvm.hexagon.M4.xor.or(i32, i32, i32)
311define i32 @M4_xor_or(i32 %a, i32 %b, i32 %c) {
312  %z = call i32 @llvm.hexagon.M4.xor.or(i32 %a, i32 %b, i32 %c)
313  ret i32 %z
314}
315; CHECK: ^= or({{.*}}, {{.*}})
316
317; Maximum words
318declare i32 @llvm.hexagon.A2.max(i32, i32)
319define i32 @A2_max(i32 %a, i32 %b) {
320  %z = call i32 @llvm.hexagon.A2.max(i32 %a, i32 %b)
321  ret i32 %z
322}
323; CHECK: = max({{.*}}, {{.*}})
324
325declare i32 @llvm.hexagon.A2.maxu(i32, i32)
326define i32 @A2_maxu(i32 %a, i32 %b) {
327  %z = call i32 @llvm.hexagon.A2.maxu(i32 %a, i32 %b)
328  ret i32 %z
329}
330; CHECK: = maxu({{.*}}, {{.*}})
331
332; Maximum doublewords
333declare i64 @llvm.hexagon.A2.maxp(i64, i64)
334define i64 @A2_maxp(i64 %a, i64 %b) {
335  %z = call i64 @llvm.hexagon.A2.maxp(i64 %a, i64 %b)
336  ret i64 %z
337}
338; CHECK: = max({{.*}}, {{.*}})
339
340declare i64 @llvm.hexagon.A2.maxup(i64, i64)
341define i64 @A2_maxup(i64 %a, i64 %b) {
342  %z = call i64 @llvm.hexagon.A2.maxup(i64 %a, i64 %b)
343  ret i64 %z
344}
345; CHECK: = maxu({{.*}}, {{.*}})
346
347; Minimum words
348declare i32 @llvm.hexagon.A2.min(i32, i32)
349define i32 @A2_min(i32 %a, i32 %b) {
350  %z = call i32 @llvm.hexagon.A2.min(i32 %a, i32 %b)
351  ret i32 %z
352}
353; CHECK: = min({{.*}}, {{.*}})
354
355declare i32 @llvm.hexagon.A2.minu(i32, i32)
356define i32 @A2_minu(i32 %a, i32 %b) {
357  %z = call i32 @llvm.hexagon.A2.minu(i32 %a, i32 %b)
358  ret i32 %z
359}
360; CHECK: = minu({{.*}}, {{.*}})
361
362; Minimum doublewords
363declare i64 @llvm.hexagon.A2.minp(i64, i64)
364define i64 @A2_minp(i64 %a, i64 %b) {
365  %z = call i64 @llvm.hexagon.A2.minp(i64 %a, i64 %b)
366  ret i64 %z
367}
368; CHECK: = min({{.*}}, {{.*}})
369
370declare i64 @llvm.hexagon.A2.minup(i64, i64)
371define i64 @A2_minup(i64 %a, i64 %b) {
372  %z = call i64 @llvm.hexagon.A2.minup(i64 %a, i64 %b)
373  ret i64 %z
374}
375; CHECK: = minu({{.*}}, {{.*}})
376
377; Module wrap
378declare i32 @llvm.hexagon.A4.modwrapu(i32, i32)
379define i32 @A4_modwrapu(i32 %a, i32 %b) {
380  %z = call i32 @llvm.hexagon.A4.modwrapu(i32 %a, i32 %b)
381  ret i32 %z
382}
383; CHECK: = modwrap({{.*}}, {{.*}})
384
385; Negate
386declare i64 @llvm.hexagon.A2.negp(i64)
387define i64 @A2_negp(i64 %a) {
388  %z = call i64 @llvm.hexagon.A2.negp(i64 %a)
389  ret i64 %z
390}
391; CHECK: = neg({{.*}})
392
393declare i32 @llvm.hexagon.A2.negsat(i32)
394define i32 @A2_negsat(i32 %a) {
395  %z = call i32 @llvm.hexagon.A2.negsat(i32 %a)
396  ret i32 %z
397}
398; CHECK: = neg({{.*}}):sat
399
400; Round
401declare i32 @llvm.hexagon.A2.roundsat(i64)
402define i32 @A2_roundsat(i64 %a) {
403  %z = call i32 @llvm.hexagon.A2.roundsat(i64 %a)
404  ret i32 %z
405}
406; CHECK: = round({{.*}}):sat
407
408declare i32 @llvm.hexagon.A4.cround.ri(i32, i32)
409define i32 @A4_cround_ri(i32 %a) {
410  %z = call i32 @llvm.hexagon.A4.cround.ri(i32 %a, i32 0)
411  ret i32 %z
412}
413; CHECK: = cround({{.*}}, #0)
414
415declare i32 @llvm.hexagon.A4.round.ri(i32, i32)
416define i32 @A4_round_ri(i32 %a) {
417  %z = call i32 @llvm.hexagon.A4.round.ri(i32 %a, i32 0)
418  ret i32 %z
419}
420; CHECK: = round({{.*}}, #0)
421
422declare i32 @llvm.hexagon.A4.round.ri.sat(i32, i32)
423define i32 @A4_round_ri_sat(i32 %a) {
424  %z = call i32 @llvm.hexagon.A4.round.ri.sat(i32 %a, i32 0)
425  ret i32 %z
426}
427; CHECK: = round({{.*}}, #0):sat
428
429declare i32 @llvm.hexagon.A4.cround.rr(i32, i32)
430define i32 @A4_cround_rr(i32 %a, i32 %b) {
431  %z = call i32 @llvm.hexagon.A4.cround.rr(i32 %a, i32 %b)
432  ret i32 %z
433}
434; CHECK: = cround({{.*}}, {{.*}})
435
436declare i32 @llvm.hexagon.A4.round.rr(i32, i32)
437define i32 @A4_round_rr(i32 %a, i32 %b) {
438  %z = call i32 @llvm.hexagon.A4.round.rr(i32 %a, i32 %b)
439  ret i32 %z
440}
441; CHECK: = round({{.*}}, {{.*}})
442
443declare i32 @llvm.hexagon.A4.round.rr.sat(i32, i32)
444define i32 @A4_round_rr_sat(i32 %a, i32 %b) {
445  %z = call i32 @llvm.hexagon.A4.round.rr.sat(i32 %a, i32 %b)
446  ret i32 %z
447}
448; CHECK: = round({{.*}}, {{.*}}):sat
449
450; Subtract doublewords
451declare i64 @llvm.hexagon.A2.subp(i64, i64)
452define i64 @A2_subp(i64 %a, i64 %b) {
453  %z = call i64 @llvm.hexagon.A2.subp(i64 %a, i64 %b)
454  ret i64 %z
455}
456; CHECK: = sub({{.*}}, {{.*}})
457
458; Subtract and accumulate
459declare i32 @llvm.hexagon.M2.subacc(i32, i32, i32)
460define i32 @M2_subacc(i32 %a, i32 %b, i32 %c) {
461  %z = call i32 @llvm.hexagon.M2.subacc(i32 %a, i32 %b, i32 %c)
462  ret i32 %z
463}
464; CHECK: += sub({{.*}}, {{.*}})
465
466; Subtract halfwords
467declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32)
468define i32 @A2_subh_l16_ll(i32 %a, i32 %b) {
469  %z = call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %a, i32 %b)
470  ret i32 %z
471}
472; CHECK: = sub({{.*}}.l, {{.*}}.l)
473
474declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32)
475define i32 @A2_subh_l16_hl(i32 %a, i32 %b) {
476  %z = call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %a, i32 %b)
477  ret i32 %z
478}
479; CHECK: = sub({{.*}}.l, {{.*}}.h)
480
481declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32)
482define i32 @A2_subh_l16_sat.ll(i32 %a, i32 %b) {
483  %z = call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %a, i32 %b)
484  ret i32 %z
485}
486; CHECK: = sub({{.*}}.l, {{.*}}.l):sat
487
488declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32)
489define i32 @A2_subh_l16_sat.hl(i32 %a, i32 %b) {
490  %z = call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %a, i32 %b)
491  ret i32 %z
492}
493; CHECK: = sub({{.*}}.l, {{.*}}.h):sat
494
495declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32)
496define i32 @A2_subh_h16_ll(i32 %a, i32 %b) {
497  %z = call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %a, i32 %b)
498  ret i32 %z
499}
500; CHECK: = sub({{.*}}.l, {{.*}}.l):<<16
501
502declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32)
503define i32 @A2_subh_h16_lh(i32 %a, i32 %b) {
504  %z = call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %a, i32 %b)
505  ret i32 %z
506}
507; CHECK: = sub({{.*}}.l, {{.*}}.h):<<16
508
509declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32)
510define i32 @A2_subh_h16_hl(i32 %a, i32 %b) {
511  %z = call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %a, i32 %b)
512  ret i32 %z
513}
514; CHECK: = sub({{.*}}.h, {{.*}}.l):<<16
515
516declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32)
517define i32 @A2_subh_h16_hh(i32 %a, i32 %b) {
518  %z = call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %a, i32 %b)
519  ret i32 %z
520}
521; CHECK: = sub({{.*}}.h, {{.*}}.h):<<16
522
523declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32)
524define i32 @A2_subh_h16_sat_ll(i32 %a, i32 %b) {
525  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %a, i32 %b)
526  ret i32 %z
527}
528; CHECK: = sub({{.*}}.l, {{.*}}.l):sat:<<16
529
530declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32)
531define i32 @A2_subh_h16_sat_lh(i32 %a, i32 %b) {
532  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %a, i32 %b)
533  ret i32 %z
534}
535; CHECK: = sub({{.*}}.l, {{.*}}.h):sat:<<16
536
537declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32)
538define i32 @A2_subh_h16_sat_hl(i32 %a, i32 %b) {
539  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %a, i32 %b)
540  ret i32 %z
541}
542; CHECK: = sub({{.*}}.h, {{.*}}.l):sat:<<16
543
544declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32)
545define i32 @A2_subh_h16_sat_hh(i32 %a, i32 %b) {
546  %z = call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %a, i32 %b)
547  ret i32 %z
548}
549; CHECK: = sub({{.*}}.h, {{.*}}.h):sat:<<16
550
551; Sign extend word to doubleword
552declare i64 @llvm.hexagon.A2.sxtw(i32)
553define i64 @A2_sxtw(i32 %a) {
554  %z = call i64 @llvm.hexagon.A2.sxtw(i32 %a)
555  ret i64 %z
556}
557; CHECK: = sxtw({{.*}})
558
559; Vector absolute value halfwords
560declare i64 @llvm.hexagon.A2.vabsh(i64)
561define i64 @A2_vabsh(i64 %a) {
562  %z = call i64 @llvm.hexagon.A2.vabsh(i64 %a)
563  ret i64 %z
564}
565; CHECK: = vabsh({{.*}})
566
567declare i64 @llvm.hexagon.A2.vabshsat(i64)
568define i64 @A2_vabshsat(i64 %a) {
569  %z = call i64 @llvm.hexagon.A2.vabshsat(i64 %a)
570  ret i64 %z
571}
572; CHECK: = vabsh({{.*}}):sat
573
574; Vector absolute value words
575declare i64 @llvm.hexagon.A2.vabsw(i64)
576define i64 @A2_vabsw(i64 %a) {
577  %z = call i64 @llvm.hexagon.A2.vabsw(i64 %a)
578  ret i64 %z
579}
580; CHECK: = vabsw({{.*}})
581
582declare i64 @llvm.hexagon.A2.vabswsat(i64)
583define i64 @A2_vabswsat(i64 %a) {
584  %z = call i64 @llvm.hexagon.A2.vabswsat(i64 %a)
585  ret i64 %z
586}
587; CHECK: = vabsw({{.*}}):sat
588
589; Vector absolute difference halfwords
590declare i64 @llvm.hexagon.M2.vabsdiffh(i64, i64)
591define i64 @M2_vabsdiffh(i64 %a, i64 %b) {
592  %z = call i64 @llvm.hexagon.M2.vabsdiffh(i64 %a, i64 %b)
593  ret i64 %z
594}
595; CHECK: = vabsdiffh({{.*}}, {{.*}})
596
597; Vector absolute difference words
598declare i64 @llvm.hexagon.M2.vabsdiffw(i64, i64)
599define i64 @M2_vabsdiffw(i64 %a, i64 %b) {
600  %z = call i64 @llvm.hexagon.M2.vabsdiffw(i64 %a, i64 %b)
601  ret i64 %z
602}
603; CHECK: = vabsdiffw({{.*}}, {{.*}})
604
605; Vector add halfwords
606declare i64 @llvm.hexagon.A2.vaddh(i64, i64)
607define i64 @A2_vaddh(i64 %a, i64 %b) {
608  %z = call i64 @llvm.hexagon.A2.vaddh(i64 %a, i64 %b)
609  ret i64 %z
610}
611; CHECK: = vaddh({{.*}}, {{.*}})
612
613declare i64 @llvm.hexagon.A2.vaddhs(i64, i64)
614define i64 @A2_vaddhs(i64 %a, i64 %b) {
615  %z = call i64 @llvm.hexagon.A2.vaddhs(i64 %a, i64 %b)
616  ret i64 %z
617}
618; CHECK: = vaddh({{.*}}, {{.*}}):sat
619
620declare i64 @llvm.hexagon.A2.vadduhs(i64, i64)
621define i64 @A2_vadduhs(i64 %a, i64 %b) {
622  %z = call i64 @llvm.hexagon.A2.vadduhs(i64 %a, i64 %b)
623  ret i64 %z
624}
625; CHECK: = vadduh({{.*}}, {{.*}}):sat
626
627; Vector add halfwords with saturate and pack to unsigned bytes
628declare i32 @llvm.hexagon.A5.vaddhubs(i64, i64)
629define i32 @A5_vaddhubs(i64 %a, i64 %b) {
630  %z = call i32 @llvm.hexagon.A5.vaddhubs(i64 %a, i64 %b)
631  ret i32 %z
632}
633; CHECK: = vaddhub({{.*}}, {{.*}}):sat
634
635; Vector reduce add unsigned bytes
636declare i64 @llvm.hexagon.A2.vraddub(i64, i64)
637define i64 @A2_vraddub(i64 %a, i64 %b) {
638  %z = call i64 @llvm.hexagon.A2.vraddub(i64 %a, i64 %b)
639  ret i64 %z
640}
641; CHECK: = vraddub({{.*}}, {{.*}})
642
643declare i64 @llvm.hexagon.A2.vraddub.acc(i64, i64, i64)
644define i64 @A2_vraddub_acc(i64 %a, i64 %b, i64 %c) {
645  %z = call i64 @llvm.hexagon.A2.vraddub.acc(i64 %a, i64 %b, i64 %c)
646  ret i64 %z
647}
648; CHECK: += vraddub({{.*}}, {{.*}})
649
650; Vector reduce add halfwords
651declare i32 @llvm.hexagon.M2.vradduh(i64, i64)
652define i32 @M2_vradduh(i64 %a, i64 %b) {
653  %z = call i32 @llvm.hexagon.M2.vradduh(i64 %a, i64 %b)
654  ret i32 %z
655}
656; CHECK: = vradduh({{.*}}, {{.*}})
657
658declare i32 @llvm.hexagon.M2.vraddh(i64, i64)
659define i32 @M2_vraddh(i64 %a, i64 %b) {
660  %z = call i32 @llvm.hexagon.M2.vraddh(i64 %a, i64 %b)
661  ret i32 %z
662}
663; CHECK: = vraddh({{.*}}, {{.*}})
664
665; Vector add bytes
666declare i64 @llvm.hexagon.A2.vaddub(i64, i64)
667define i64 @A2_vaddub(i64 %a, i64 %b) {
668  %z = call i64 @llvm.hexagon.A2.vaddub(i64 %a, i64 %b)
669  ret i64 %z
670}
671; CHECK: = vaddub({{.*}}, {{.*}})
672
673declare i64 @llvm.hexagon.A2.vaddubs(i64, i64)
674define i64 @A2_vaddubs(i64 %a, i64 %b) {
675  %z = call i64 @llvm.hexagon.A2.vaddubs(i64 %a, i64 %b)
676  ret i64 %z
677}
678; CHECK: = vaddub({{.*}}, {{.*}}):sat
679
680; Vector add words
681declare i64 @llvm.hexagon.A2.vaddw(i64, i64)
682define i64 @A2_vaddw(i64 %a, i64 %b) {
683  %z = call i64 @llvm.hexagon.A2.vaddw(i64 %a, i64 %b)
684  ret i64 %z
685}
686; CHECK: = vaddw({{.*}}, {{.*}})
687
688declare i64 @llvm.hexagon.A2.vaddws(i64, i64)
689define i64 @A2_vaddws(i64 %a, i64 %b) {
690  %z = call i64 @llvm.hexagon.A2.vaddws(i64 %a, i64 %b)
691  ret i64 %z
692}
693; CHECK: = vaddw({{.*}}, {{.*}}):sat
694
695; Vector average halfwords
696declare i64 @llvm.hexagon.A2.vavgh(i64, i64)
697define i64 @A2_vavgh(i64 %a, i64 %b) {
698  %z = call i64 @llvm.hexagon.A2.vavgh(i64 %a, i64 %b)
699  ret i64 %z
700}
701; CHECK: = vavgh({{.*}}, {{.*}})
702
703declare i64 @llvm.hexagon.A2.vavghr(i64, i64)
704define i64 @A2_vavghr(i64 %a, i64 %b) {
705  %z = call i64 @llvm.hexagon.A2.vavghr(i64 %a, i64 %b)
706  ret i64 %z
707}
708; CHECK: = vavgh({{.*}}, {{.*}}):rnd
709
710declare i64 @llvm.hexagon.A2.vavghcr(i64, i64)
711define i64 @A2_vavghcr(i64 %a, i64 %b) {
712  %z = call i64 @llvm.hexagon.A2.vavghcr(i64 %a, i64 %b)
713  ret i64 %z
714}
715; CHECK: = vavgh({{.*}}, {{.*}}):crnd
716
717declare i64 @llvm.hexagon.A2.vavguh(i64, i64)
718define i64 @A2_vavguh(i64 %a, i64 %b) {
719  %z = call i64 @llvm.hexagon.A2.vavguh(i64 %a, i64 %b)
720  ret i64 %z
721}
722; CHECK: = vavguh({{.*}}, {{.*}})
723
724declare i64 @llvm.hexagon.A2.vavguhr(i64, i64)
725define i64 @A2_vavguhr(i64 %a, i64 %b) {
726  %z = call i64 @llvm.hexagon.A2.vavguhr(i64 %a, i64 %b)
727  ret i64 %z
728}
729; CHECK: = vavguh({{.*}}, {{.*}}):rnd
730
731declare i64 @llvm.hexagon.A2.vnavgh(i64, i64)
732define i64 @A2_vnavgh(i64 %a, i64 %b) {
733  %z = call i64 @llvm.hexagon.A2.vnavgh(i64 %a, i64 %b)
734  ret i64 %z
735}
736; CHECK: = vnavgh({{.*}}, {{.*}})
737
738declare i64 @llvm.hexagon.A2.vnavghr(i64, i64)
739define i64 @A2_vnavghr(i64 %a, i64 %b) {
740  %z = call i64 @llvm.hexagon.A2.vnavghr(i64 %a, i64 %b)
741  ret i64 %z
742}
743; CHECK: = vnavgh({{.*}}, {{.*}}):rnd
744
745declare i64 @llvm.hexagon.A2.vnavghcr(i64, i64)
746define i64 @A2_vnavghcr(i64 %a, i64 %b) {
747  %z = call i64 @llvm.hexagon.A2.vnavghcr(i64 %a, i64 %b)
748  ret i64 %z
749}
750; CHECK: = vnavgh({{.*}}, {{.*}}):crnd
751
752; Vector average unsigned bytes
753declare i64 @llvm.hexagon.A2.vavgub(i64, i64)
754define i64 @A2_vavgub(i64 %a, i64 %b) {
755  %z = call i64 @llvm.hexagon.A2.vavgub(i64 %a, i64 %b)
756  ret i64 %z
757}
758; CHECK:  vavgub({{.*}}, {{.*}})
759
760declare i64 @llvm.hexagon.A2.vavgubr(i64, i64)
761define i64 @A2_vavgubr(i64 %a, i64 %b) {
762  %z = call i64 @llvm.hexagon.A2.vavgubr(i64 %a, i64 %b)
763  ret i64 %z
764}
765; CHECK: = vavgub({{.*}}, {{.*}}):rnd
766
767; Vector average words
768declare i64 @llvm.hexagon.A2.vavgw(i64, i64)
769define i64 @A2_vavgw(i64 %a, i64 %b) {
770  %z = call i64 @llvm.hexagon.A2.vavgw(i64 %a, i64 %b)
771  ret i64 %z
772}
773; CHECK: = vavgw({{.*}}, {{.*}})
774
775declare i64 @llvm.hexagon.A2.vavgwr(i64, i64)
776define i64 @A2_vavgwr(i64 %a, i64 %b) {
777  %z = call i64 @llvm.hexagon.A2.vavgwr(i64 %a, i64 %b)
778  ret i64 %z
779}
780; CHECK: = vavgw({{.*}}, {{.*}}):rnd
781
782declare i64 @llvm.hexagon.A2.vavgwcr(i64, i64)
783define i64 @A2_vavgwcr(i64 %a, i64 %b) {
784  %z = call i64 @llvm.hexagon.A2.vavgwcr(i64 %a, i64 %b)
785  ret i64 %z
786}
787; CHECK: = vavgw({{.*}}, {{.*}}):crnd
788
789declare i64 @llvm.hexagon.A2.vavguw(i64, i64)
790define i64 @A2_vavguw(i64 %a, i64 %b) {
791  %z = call i64 @llvm.hexagon.A2.vavguw(i64 %a, i64 %b)
792  ret i64 %z
793}
794; CHECK: = vavguw({{.*}}, {{.*}})
795
796declare i64 @llvm.hexagon.A2.vavguwr(i64, i64)
797define i64 @A2_vavguwr(i64 %a, i64 %b) {
798  %z = call i64 @llvm.hexagon.A2.vavguwr(i64 %a, i64 %b)
799  ret i64 %z
800}
801; CHECK: = vavguw({{.*}}, {{.*}}):rnd
802
803declare i64 @llvm.hexagon.A2.vnavgw(i64, i64)
804define i64 @A2_vnavgw(i64 %a, i64 %b) {
805  %z = call i64 @llvm.hexagon.A2.vnavgw(i64 %a, i64 %b)
806  ret i64 %z
807}
808; CHECK: = vnavgw({{.*}}, {{.*}})
809
810declare i64 @llvm.hexagon.A2.vnavgwr(i64, i64)
811define i64 @A2_vnavgwr(i64 %a, i64 %b) {
812  %z = call i64 @llvm.hexagon.A2.vnavgwr(i64 %a, i64 %b)
813  ret i64 %z
814}
815; CHECK: = vnavgw({{.*}}, {{.*}}):rnd
816
817declare i64 @llvm.hexagon.A2.vnavgwcr(i64, i64)
818define i64 @A2_vnavgwcr(i64 %a, i64 %b) {
819  %z = call i64 @llvm.hexagon.A2.vnavgwcr(i64 %a, i64 %b)
820  ret i64 %z
821}
822; CHECK: = vnavgw({{.*}}, {{.*}}):crnd
823
824; Vector conditional negate
825declare i64 @llvm.hexagon.S2.vcnegh(i64, i32)
826define i64 @S2_vcnegh(i64 %a, i32 %b) {
827  %z = call i64 @llvm.hexagon.S2.vcnegh(i64 %a, i32 %b)
828  ret i64 %z
829}
830; CHECK: = vcnegh({{.*}}, {{.*}})
831
832declare i64 @llvm.hexagon.S2.vrcnegh(i64, i64, i32)
833define i64 @S2_vrcnegh(i64 %a, i64 %b, i32 %c) {
834  %z = call i64 @llvm.hexagon.S2.vrcnegh(i64 %a, i64 %b, i32 %c)
835  ret i64 %z
836}
837; CHECK: += vrcnegh({{.*}}, {{.*}})
838
839; Vector maximum bytes
840declare i64 @llvm.hexagon.A2.vmaxub(i64, i64)
841define i64 @A2_vmaxub(i64 %a, i64 %b) {
842  %z = call i64 @llvm.hexagon.A2.vmaxub(i64 %a, i64 %b)
843  ret i64 %z
844}
845; CHECK: = vmaxub({{.*}}, {{.*}})
846
847declare i64 @llvm.hexagon.A2.vmaxb(i64, i64)
848define i64 @A2_vmaxb(i64 %a, i64 %b) {
849  %z = call i64 @llvm.hexagon.A2.vmaxb(i64 %a, i64 %b)
850  ret i64 %z
851}
852; CHECK: = vmaxb({{.*}}, {{.*}})
853
854; Vector maximum halfwords
855declare i64 @llvm.hexagon.A2.vmaxh(i64, i64)
856define i64 @A2_vmaxh(i64 %a, i64 %b) {
857  %z = call i64 @llvm.hexagon.A2.vmaxh(i64 %a, i64 %b)
858  ret i64 %z
859}
860; CHECK: = vmaxh({{.*}}, {{.*}})
861
862declare i64 @llvm.hexagon.A2.vmaxuh(i64, i64)
863define i64 @A2_vmaxuh(i64 %a, i64 %b) {
864  %z = call i64 @llvm.hexagon.A2.vmaxuh(i64 %a, i64 %b)
865  ret i64 %z
866}
867; CHECK: = vmaxuh({{.*}}, {{.*}})
868
869; Vector reduce maximum halfwords
870declare i64 @llvm.hexagon.A4.vrmaxh(i64, i64, i32)
871define i64 @A4_vrmaxh(i64 %a, i64 %b, i32 %c) {
872  %z = call i64 @llvm.hexagon.A4.vrmaxh(i64 %a, i64 %b, i32 %c)
873  ret i64 %z
874}
875; CHECK: = vrmaxh({{.*}}, {{.*}})
876
877declare i64 @llvm.hexagon.A4.vrmaxuh(i64, i64, i32)
878define i64 @A4_vrmaxuh(i64 %a, i64 %b, i32 %c) {
879  %z = call i64 @llvm.hexagon.A4.vrmaxuh(i64 %a, i64 %b, i32 %c)
880  ret i64 %z
881}
882; CHECK: = vrmaxuh({{.*}}, {{.*}})
883
884; Vector reduce maximum words
885declare i64 @llvm.hexagon.A4.vrmaxw(i64, i64, i32)
886define i64 @A4_vrmaxw(i64 %a, i64 %b, i32 %c) {
887  %z = call i64 @llvm.hexagon.A4.vrmaxw(i64 %a, i64 %b, i32 %c)
888  ret i64 %z
889}
890; CHECK: = vrmaxw({{.*}}, {{.*}})
891
892declare i64 @llvm.hexagon.A4.vrmaxuw(i64, i64, i32)
893define i64 @A4_vrmaxuw(i64 %a, i64 %b, i32 %c) {
894  %z = call i64 @llvm.hexagon.A4.vrmaxuw(i64 %a, i64 %b, i32 %c)
895  ret i64 %z
896}
897; CHECK:  vrmaxuw({{.*}}, {{.*}})
898
899; Vector minimum bytes
900declare i64 @llvm.hexagon.A2.vminub(i64, i64)
901define i64 @A2_vminub(i64 %a, i64 %b) {
902  %z = call i64 @llvm.hexagon.A2.vminub(i64 %a, i64 %b)
903  ret i64 %z
904}
905; CHECK: = vminub({{.*}}, {{.*}})
906
907declare i64 @llvm.hexagon.A2.vminb(i64, i64)
908define i64 @A2_vminb(i64 %a, i64 %b) {
909  %z = call i64 @llvm.hexagon.A2.vminb(i64 %a, i64 %b)
910  ret i64 %z
911}
912; CHECK: = vminb({{.*}}, {{.*}})
913
914; Vector minimum halfwords
915declare i64 @llvm.hexagon.A2.vminh(i64, i64)
916define i64 @A2_vminh(i64 %a, i64 %b) {
917  %z = call i64 @llvm.hexagon.A2.vminh(i64 %a, i64 %b)
918  ret i64 %z
919}
920; CHECK: = vminh({{.*}}, {{.*}})
921
922declare i64 @llvm.hexagon.A2.vminuh(i64, i64)
923define i64 @A2_vminuh(i64 %a, i64 %b) {
924  %z = call i64 @llvm.hexagon.A2.vminuh(i64 %a, i64 %b)
925  ret i64 %z
926}
927; CHECK: = vminuh({{.*}}, {{.*}})
928
929; Vector reduce minimum halfwords
930declare i64 @llvm.hexagon.A4.vrminh(i64, i64, i32)
931define i64 @A4_vrminh(i64 %a, i64 %b, i32 %c) {
932  %z = call i64 @llvm.hexagon.A4.vrminh(i64 %a, i64 %b, i32 %c)
933  ret i64 %z
934}
935; CHECK: = vrminh({{.*}}, {{.*}})
936
937declare i64 @llvm.hexagon.A4.vrminuh(i64, i64, i32)
938define i64 @A4_vrminuh(i64 %a, i64 %b, i32 %c) {
939  %z = call i64 @llvm.hexagon.A4.vrminuh(i64 %a, i64 %b, i32 %c)
940  ret i64 %z
941}
942; CHECK: = vrminuh({{.*}}, {{.*}})
943
944; Vector reduce minimum words
945declare i64 @llvm.hexagon.A4.vrminw(i64, i64, i32)
946define i64 @A4_vrminw(i64 %a, i64 %b, i32 %c) {
947  %z = call i64 @llvm.hexagon.A4.vrminw(i64 %a, i64 %b, i32 %c)
948  ret i64 %z
949}
950; CHECK: = vrminw({{.*}}, {{.*}})
951
952declare i64 @llvm.hexagon.A4.vrminuw(i64, i64, i32)
953define i64 @A4_vrminuw(i64 %a, i64 %b, i32 %c) {
954  %z = call i64 @llvm.hexagon.A4.vrminuw(i64 %a, i64 %b, i32 %c)
955  ret i64 %z
956}
957; CHECK: = vrminuw({{.*}}, {{.*}})
958
959; Vector sum of absolute differences unsigned bytes
960declare i64 @llvm.hexagon.A2.vrsadub(i64, i64)
961define i64 @A2_vrsadub(i64 %a, i64 %b) {
962  %z = call i64 @llvm.hexagon.A2.vrsadub(i64 %a, i64 %b)
963  ret i64 %z
964}
965; CHECK: = vrsadub({{.*}}, {{.*}})
966
967declare i64 @llvm.hexagon.A2.vrsadub.acc(i64, i64, i64)
968define i64 @A2_vrsadub_acc(i64 %a, i64 %b, i64 %c) {
969  %z = call i64 @llvm.hexagon.A2.vrsadub.acc(i64 %a, i64 %b, i64 %c)
970  ret i64 %z
971}
972; CHECK: += vrsadub({{.*}}, {{.*}})
973
974; Vector subtract halfwords
975declare i64 @llvm.hexagon.A2.vsubh(i64, i64)
976define i64 @A2_vsubh(i64 %a, i64 %b) {
977  %z = call i64 @llvm.hexagon.A2.vsubh(i64 %a, i64 %b)
978  ret i64 %z
979}
980; CHECK: = vsubh({{.*}}, {{.*}})
981
982declare i64 @llvm.hexagon.A2.vsubhs(i64, i64)
983define i64 @A2_vsubhs(i64 %a, i64 %b) {
984  %z = call i64 @llvm.hexagon.A2.vsubhs(i64 %a, i64 %b)
985  ret i64 %z
986}
987; CHECK: = vsubh({{.*}}, {{.*}}):sat
988
989declare i64 @llvm.hexagon.A2.vsubuhs(i64, i64)
990define i64 @A2_vsubuhs(i64 %a, i64 %b) {
991  %z = call i64 @llvm.hexagon.A2.vsubuhs(i64 %a, i64 %b)
992  ret i64 %z
993}
994; CHECK: = vsubuh({{.*}}, {{.*}}):sat
995
996; Vector subtract bytes
997declare i64 @llvm.hexagon.A2.vsubub(i64, i64)
998define i64 @A2_vsubub(i64 %a, i64 %b) {
999  %z = call i64 @llvm.hexagon.A2.vsubub(i64 %a, i64 %b)
1000  ret i64 %z
1001}
1002; CHECK: = vsubub({{.*}}, {{.*}})
1003
1004declare i64 @llvm.hexagon.A2.vsububs(i64, i64)
1005define i64 @A2_vsububs(i64 %a, i64 %b) {
1006  %z = call i64 @llvm.hexagon.A2.vsububs(i64 %a, i64 %b)
1007  ret i64 %z
1008}
1009; CHECK: = vsubub({{.*}}, {{.*}}):sat
1010
1011; Vector subtract words
1012declare i64 @llvm.hexagon.A2.vsubw(i64, i64)
1013define i64 @A2_vsubw(i64 %a, i64 %b) {
1014  %z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b)
1015  ret i64 %z
1016}
1017; CHECK: = vsubw({{.*}}, {{.*}})
1018
1019declare i64 @llvm.hexagon.A2.vsubws(i64, i64)
1020define i64 @A2_vsubws(i64 %a, i64 %b) {
1021  %z = call i64 @llvm.hexagon.A2.vsubws(i64 %a, i64 %b)
1022  ret i64 %z
1023}
1024; CHECK: = vsubw({{.*}}, {{.*}}):sat
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