1 | /* Block Addition, Subtraction and Shifts with Carry |
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2 | Copyright (C) 2010, Robert D. Cameron |
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3 | Licensed to the public under the Open Software License 3.0. |
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4 | Licensed to International Characters Inc. |
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5 | under the Academic Free License version 3.0. |
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6 | |
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7 | This file defines addition, subtract and shift operations on |
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8 | 128-bit blocks. Different versions of the operations are |
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9 | selectable with the CARRY_STRATEGY preprocessor constant. |
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10 | |
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11 | Each implementation defines the following "abstract data type" |
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12 | for block operations with carry. |
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13 | |
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14 | Typename: CarryType |
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15 | Constant: Carry0 represents a value of 0 for the carry bit. |
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16 | Predicate: test_carry(x) returns nonzero if a carry bit is 1, 0 otherwise. |
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17 | Function: carry_or(carry1, carry2) forms the logical or of two carries. |
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18 | Function: adc128(x, y, carry, sum) computes (carry, sum) = x + y + carry, |
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19 | Function: advance_with_carry(cursor, carry, rslt) |
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20 | computes (carry, rslt) = cursor + cursor + carry |
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21 | Function: sbb128(x, y, borrow, diff) |
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22 | computes (borrow, diff) = y - x - borrow |
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23 | |
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24 | */ |
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25 | #ifndef BLOCK_CARRY_H |
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26 | #define BLOCK_CARRY_H |
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27 | |
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28 | |
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29 | typedef union {SIMD_type bitblock; uint64_t int64[2];} BitBlock_int64; |
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30 | |
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31 | |
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32 | |
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33 | /*------------------------------------------------------------*/ |
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34 | #include "sse_simd.h" |
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35 | |
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36 | #define SIMD_CARRY_STRATEGY 1 |
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37 | #define ADC64_STRATEGY 2 |
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38 | |
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39 | #ifdef ADC64 |
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40 | #define CARRY_STRATEGY ADC64_STRATEGY |
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41 | #else |
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42 | #define CARRY_STRATEGY SIMD_CARRY_STRATEGY |
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43 | #endif |
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44 | |
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45 | #if (CARRY_STRATEGY == ADC64_STRATEGY) |
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46 | typedef uint64_t CarryType; |
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47 | |
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48 | #define Carry0 0 |
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49 | |
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50 | #define carry_flip(c) ((c) ^ 1) |
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51 | |
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52 | #define test_carry(x) ((x) > 0) |
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53 | |
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54 | #define carry_or(carry1, carry2) (carry1 | carry2) |
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55 | |
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56 | #define adc(x,y,carry,sum) \ |
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57 | __asm__ __volatile__ ("add %[carryflag], %[e]\n\t" \ |
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58 | "adc %[e], %[z]\n\t" \ |
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59 | "mov $0, %1\n\t" \ |
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60 | "adc %[carryflag], %1\n\t" \ |
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61 | : [z] "=r" (sum), [carryflag] "=a" (carry) \ |
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62 | : "[z]" (x), [e] "r" (y), "[carryflag]" (carry) \ |
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63 | : "cc") |
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64 | |
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65 | #define double_int64_adc(x1, x2, y1, y2, rslt1, rslt2, carry) \ |
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66 | __asm__ __volatile__ ("neg %[carryflag]\n\t" \ |
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67 | "adc %[e1], %[z1]\n\t" \ |
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68 | "adc %[e2], %[z2]\n\t" \ |
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69 | "mov $0, %[carryflag]\n\t" \ |
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70 | "adc $0, %[carryflag]\n\t" \ |
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71 | : [z1] "=r" (rslt1), [z2] "=r" (rslt2), [carryflag] "=r" (carry) \ |
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72 | : "[z1]" (x1), "[z2]" (x2), \ |
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73 | [e1] "r" (y1), [e2] "r" (y2), \ |
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74 | "[carryflag]" (carry) \ |
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75 | : "cc") |
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76 | |
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77 | |
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78 | #define adc128(first, second, carry, sum) \ |
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79 | do {\ |
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80 | BitBlock_int64 rslt, x, y;\ |
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81 | x.bitblock = first;\ |
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82 | y.bitblock = second;\ |
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83 | double_int64_adc(x.int64[0], x.int64[1], y.int64[0], y.int64[1], rslt.int64[0], rslt.int64[1], carry);\ |
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84 | sum = rslt.bitblock;\ |
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85 | } while(0) |
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86 | |
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87 | |
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88 | |
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89 | #define double_int64_advance(x1, x2, rslt1, rslt2, carry) \ |
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90 | __asm__ (\ |
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91 | "add %[z1], %[z1]\n\t" \ |
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92 | "adc %[z2], %[z2]\n\t" \ |
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93 | "lea 0(%[carryflag], %[z1]), %[z1]\n\t" \ |
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94 | "setc %%al\n\t" \ |
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95 | : [z1] "=r" (rslt1), [z2] "=r" (rslt2), [carryflag] "=a" (carry) \ |
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96 | : "[z1]" (x1), "[z2]" (x2), \ |
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97 | "[carryflag]" (carry) \ |
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98 | : "cc") |
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99 | |
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100 | /* Slow |
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101 | #define double_int64_advance(x1, x2, rslt1, rslt2, carry) \ |
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102 | __asm__ (\ |
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103 | "shld $1, %[z1], %[z2]\n\t" \ |
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104 | "lea 0(%[carryflag], %[z1], 2), %[z1]\n\t" \ |
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105 | "setc %%al\n\t" \ |
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106 | : [z1] "=r" (rslt1), [z2] "=r" (rslt2), [carryflag] "=a" (carry) \ |
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107 | : "[z1]" (x1), "[z2]" (x2), \ |
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108 | "[carryflag]" (carry) \ |
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109 | : "cc") |
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110 | */ |
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111 | |
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112 | #define advance_with_carry(cursor, carry, rslt)\ |
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113 | do {\ |
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114 | BitBlock_int64 x, z;\ |
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115 | x.bitblock = cursor;\ |
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116 | double_int64_advance(x.int64[0], x.int64[1], z.int64[0], z.int64[1], carry);\ |
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117 | rslt = z.bitblock;\ |
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118 | } while(0) |
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119 | |
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120 | #define double_int64_sbb(x1, x2, y1, y2, rslt1, rslt2, brw) \ |
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121 | __asm__ ("neg %[borrowflag]\n\t" \ |
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122 | "sbb %[e1], %[z1]\n\t" \ |
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123 | "sbb %[e2], %[z2]\n\t" \ |
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124 | "mov $0, %[borrowflag]\n\t" \ |
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125 | "sbb $0, %[borrowflag]\n\t" \ |
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126 | : [z1] "=r" (rslt1), [z2] "=r" (rslt2), [borrowflag] "=a" (brw) \ |
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127 | : "[z1]" (x1), "[z2]" (x2), \ |
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128 | [e1] "r" (y1), [e2] "r" (y2), \ |
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129 | "[borrowflag]" (brw) \ |
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130 | : "cc") |
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131 | |
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132 | #define sbb128(first, second, borrow, diff) \ |
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133 | do {\ |
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134 | BitBlock_int64 rslt, x, y;\ |
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135 | x.bitblock = first;\ |
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136 | y.bitblock = second;\ |
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137 | double_int64_sbb(x.int64[0], x.int64[1], y.int64[0], y.int64[1], \ |
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138 | rslt.int64[0], rslt.int64[1], borrow);\ |
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139 | diff = rslt.bitblock;\ |
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140 | } while(0) |
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141 | |
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142 | |
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143 | #endif |
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144 | |
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145 | |
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146 | |
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147 | #if (CARRY_STRATEGY == SIMD_CARRY_STRATEGY) |
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148 | |
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149 | typedef SIMD_type CarryType; |
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150 | |
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151 | #define Carry0 simd_const_1(0) |
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152 | |
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153 | #define carry_flip(c) simd_xor(c, sisd_from_int(1)) |
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154 | |
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155 | #define test_carry(x) bitblock_has_bit(x) |
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156 | |
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157 | #define carry_or(carry1, carry2) simd_or(carry1, carry2) |
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158 | |
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159 | #define adc128(x, y, carry, sum) \ |
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160 | do{ \ |
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161 | SIMD_type gen = simd_and(x, y); \ |
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162 | SIMD_type prop = simd_or(x, y); \ |
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163 | SIMD_type partial = simd_add_64(simd_add_64(x, y), carry); \ |
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164 | SIMD_type c1 = sisd_slli(simd_srli_64(simd_or(gen, simd_andc(prop, partial)), 63), 64); \ |
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165 | sum = simd_add_64(c1, partial); \ |
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166 | carry = sisd_srli(simd_or(gen, simd_andc(prop, sum)), 127); \ |
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167 | } while(0) |
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168 | |
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169 | |
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170 | #define sbb128(x, y, borrow, difference) \ |
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171 | do {\ |
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172 | SIMD_type gen = simd_andc(y, x); \ |
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173 | SIMD_type prop = simd_not(simd_xor(x, y)); \ |
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174 | SIMD_type partial = simd_sub_64(simd_sub_64(x, y), borrow); \ |
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175 | SIMD_type b1 = sisd_slli(simd_srli_64(simd_or(gen, simd_and(prop, partial)), 63), 64); \ |
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176 | difference = simd_sub_64(partial, b1); \ |
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177 | borrow = sisd_srli(simd_or(gen, simd_and(prop, difference)), 127); \ |
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178 | }while(0) |
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179 | |
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180 | |
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181 | #define advance_with_carry(cursor, carry, rslt)\ |
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182 | do {\ |
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183 | SIMD_type shift_out = simd_srli_64(cursor, 63);\ |
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184 | SIMD_type low_bits = simd_mergel_64(shift_out, carry);\ |
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185 | carry = sisd_srli(shift_out, 64);\ |
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186 | rslt = simd_or(simd_add_64(cursor, cursor), low_bits);\ |
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187 | } while(0) |
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188 | |
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189 | #endif |
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190 | #endif |
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191 | |
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192 | |
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