1 | /* x86_CPU_detect.h: Run-Time Detection of x86 and x86_64 SIMD features. |
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2 | |
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3 | Copyright (C) 2010, Robert D. Cameron |
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4 | Licensed under Academic Free License version 3.0. |
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5 | |
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6 | You may freely #include this file in software that is public |
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7 | domain or licensed under any open source or other license. |
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8 | |
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9 | This file defines the following functions which perform |
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10 | runtime tests to see if particular SIMD or other acceleration |
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11 | features are supported on x86 and x86-64 architectures. |
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12 | The functions return 0 if a feature is not supported, a nonzero value, |
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13 | otherwise. |
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14 | |
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15 | CPU_has_MMX() |
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16 | CPU_has_SSE() |
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17 | CPU_has_SSE2() |
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18 | CPU_has_SSE3() |
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19 | CPU_has_SSSE3() |
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20 | CPU_has_SSE41() |
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21 | CPU_has_SSE42() |
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22 | CPU_has_AVX() |
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23 | CPU_has_POPCOUNT() |
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24 | |
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25 | The CPUID instruction is used to determine these features, |
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26 | taking advantage of the appropriate __cpuid compiler intrinsic |
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27 | available with GCC and MSVC compilers. |
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28 | |
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29 | Principal objective: Dynamic detection of SIMD processor |
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30 | capabilities is required when software is to be compiled |
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31 | to produce a binary that is compatible with a range of |
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32 | processors, including: |
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33 | (a) some processors with no SIMD capabilities, |
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34 | (b) some processors with a particular restricted subset |
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35 | of SIMD capabilities (e.g., SSE but not SSE2), and |
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36 | (c) some processors with the full set of desired SIMD |
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37 | capabilities. |
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38 | |
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39 | Compilation note: The detection code must run successfully on |
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40 | processors having no SIMD capabilities. Therefore, this module must |
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41 | be compiled without any compiler flags such as -msse2 or the like. |
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42 | */ |
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43 | |
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44 | #ifndef X86_CPU_DETECT_H |
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45 | #define X86_CPU_DETECT_H |
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46 | |
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47 | /* These routines are for the Intel/AMD x86 (32-bit) and x86-64 (64-bit) |
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48 | architectures. Ensure that we are compiling for one of these |
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49 | architectures. Define common macros x86_32 and x86_64 based on |
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50 | known compiler-specific macros for these architectures. |
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51 | See http://predef.sourceforge.net/prearch.html |
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52 | */ |
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53 | |
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54 | #if defined(__x86_64__) || defined(_M_X64) |
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55 | #define x86_64 1 |
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56 | #elif defined(__i386__) || defined(_M_IX86) || defined(__i386) || defined(__THW_INTEL__) |
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57 | #define x86_32 1 |
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58 | #endif |
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59 | |
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60 | #if defined(x86_32) || defined(x86_64) |
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61 | |
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62 | enum CPUid_reg { |
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63 | reg_eax = 0, |
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64 | reg_ebx = 1, |
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65 | reg_ecx = 2, |
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66 | reg_edx = 3 |
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67 | }; |
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68 | |
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69 | #ifdef _MSC_VER |
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70 | #include <intrin.h> |
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71 | static inline int check_CPUid1_feature(enum CPUid_reg reg, int CPUid_bit) { |
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72 | int CPUinfo[4]; |
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73 | __cpuid(CPUinfo, 1); |
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74 | return CPUinfo[reg] & CPUid_bit; |
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75 | } |
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76 | #endif |
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77 | |
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78 | #ifdef __GNUC__ |
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79 | #include <cpuid.h> |
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80 | static inline int check_CPUid1_feature(enum CPUid_reg reg, int CPUid_bit) { |
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81 | unsigned int CPUinfo[4]; |
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82 | if (__get_cpuid(1, &CPUinfo[reg_eax], &CPUinfo[reg_ebx], &CPUinfo[reg_ecx], &CPUinfo[reg_edx])) |
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83 | return CPUinfo[reg] & CPUid_bit; |
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84 | else return 0; |
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85 | } |
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86 | #endif |
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87 | |
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88 | |
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89 | #define MMX_CPUid_feature_register reg_edx |
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90 | #define MMX_CPUid_feature_bit (1 << 23) |
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91 | |
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92 | #define SSE_CPUid_feature_register reg_edx |
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93 | #define SSE_CPUid_feature_bit (1 << 25) |
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94 | |
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95 | #define SSE2_CPUid_feature_register reg_edx |
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96 | #define SSE2_CPUid_feature_bit (1 << 26) |
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97 | |
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98 | #define SSE3_CPUid_feature_register reg_ecx |
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99 | #define SSE3_CPUid_feature_bit (1 << 0) |
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100 | |
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101 | #define SSSE3_CPUid_feature_register reg_ecx |
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102 | #define SSSE3_CPUid_feature_bit (1 << 9) |
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103 | |
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104 | #define SSE41_CPUid_feature_register reg_ecx |
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105 | #define SSE41_CPUid_feature_bit (1 << 19) |
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106 | |
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107 | #define SSE42_CPUid_feature_register reg_ecx |
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108 | #define SSE42_CPUid_feature_bit (1 << 20) |
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109 | |
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110 | #define AVX_CPUid_feature_register reg_ecx |
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111 | #define AVX_CPUid_feature_bit (1 << 28) |
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112 | |
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113 | #define POPCOUNT_CPUid_feature_register reg_ecx |
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114 | #define POPCOUNT_CPUid_feature_bit (1 << 23) |
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115 | |
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116 | |
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117 | static inline int CPU_has_MMX() { |
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118 | #ifdef x86_64 |
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119 | return MMX_CPUid_feature_bit; /* MMX always available on x86_64 */ |
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120 | #else |
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121 | return check_CPUid1_feature(MMX_CPUid_feature_register, MMX_CPUid_feature_bit); |
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122 | #endif |
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123 | } |
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124 | static inline int CPU_has_SSE() { |
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125 | #ifdef x86_64 |
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126 | return SSE_CPUid_feature_bit; /* SSE always available on x86_64 */ |
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127 | #else |
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128 | return check_CPUid1_feature(SSE_CPUid_feature_register, SSE_CPUid_feature_bit); |
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129 | #endif |
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130 | } |
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131 | static inline int CPU_has_SSE2() { |
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132 | #ifdef x86_64 |
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133 | return SSE2_CPUid_feature_bit; /* SSE2 always available on x86_64 */ |
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134 | #else |
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135 | return check_CPUid1_feature(SSE2_CPUid_feature_register, SSE2_CPUid_feature_bit); |
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136 | #endif |
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137 | } |
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138 | |
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139 | static inline int CPU_has_SSE3() { |
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140 | return check_CPUid1_feature(SSE3_CPUid_feature_register, SSE3_CPUid_feature_bit); |
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141 | } |
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142 | |
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143 | static inline int CPU_has_SSSE3() { |
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144 | return check_CPUid1_feature(SSSE3_CPUid_feature_register, SSSE3_CPUid_feature_bit); |
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145 | } |
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146 | |
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147 | static inline int CPU_has_SSE41() { |
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148 | return check_CPUid1_feature(SSE41_CPUid_feature_register, SSE41_CPUid_feature_bit); |
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149 | } |
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150 | |
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151 | static inline int CPU_has_SSE42() { |
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152 | return check_CPUid1_feature(SSE42_CPUid_feature_register, SSE42_CPUid_feature_bit); |
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153 | } |
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154 | |
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155 | static inline int CPU_has_AVX() { |
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156 | return check_CPUid1_feature(AVX_CPUid_feature_register, AVX_CPUid_feature_bit); |
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157 | } |
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158 | |
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159 | static inline int CPU_has_POPCOUNT() { |
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160 | return check_CPUid1_feature(POPCOUNT_CPUid_feature_register, POPCOUNT_CPUid_feature_bit); |
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161 | } |
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162 | |
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163 | #endif |
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164 | #endif |
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