Changeset 1023 for docs/PACT2011


Ignore:
Timestamp:
Mar 25, 2011, 6:42:14 PM (8 years ago)
Author:
cameron
Message:

Updated main with conclusions

Location:
docs/PACT2011
Files:
2 edited

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  • docs/PACT2011/08-conclusions.tex

    r969 r1023  
    11\section{Conclusion}
    22
     3This paper has examined energy efficiency and performance
     4characteristics of four XML parsers considered over three
     5generations of Intel processor architecture and shown that
     6parsers based on parallel bit stream technology have dramatically
     7better performance, energy efficiency and scalability than
     8traditional byte-at-a-time parsers widely deployed in current
     9software.  Based on a novel application of the short vector
     10SIMD technology commonly found in commodity processors of
     11all kinds, parallel bit stream technology scales well with
     12improvements in processor SIMD capabilities.  With the recent
     13introduction of the first generation of Intel processors that
     14incorporate AVX technology, the change to 3-operand
     15form SIMD operations has delivered a substantial benefit
     16for the Parabix2 parsers simply through recompilation.
     17Restructuring of Parabix2 to take advantage of the 256-bit SIMD
     18capabilities also delivered a substantial reduction in
     19instruction count, but without corresponding performance
     20benefits in the first generation of AVX implementations.
     21
     22There are many directions for further research.   These
     23include compiler and tools technology to automate the low-level
     24programming tasks inherent in building parallel bit stream
     25applications, widening the research by applying the techniques
     26to other forms of text analysis and parsing, and further
     27investigation of the interaction between parallel bit
     28stream technology and processor architecture.  Two promising
     29avenues include investigation of GPGPU approaches to parallel
     30bit stream technology and the leveraging of the intraregister parallelism
     31inherent in this approach to also take advantage of the intrachip
     32parallelism of multicore processors.
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