Changeset 1078


Ignore:
Timestamp:
Apr 8, 2011, 2:31:22 PM (8 years ago)
Author:
ksherdy
Message:

Update macros \CI to \CI3

Location:
docs/PACT2011
Files:
5 edited

Legend:

Unmodified
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  • docs/PACT2011/01-intro.tex

    r1039 r1078  
    7979for the performance and energy study tackled in the
    8080remainder of the paper.   Section 5 presents a
    81 detailed performance evaluation on a \CI\ processor
     81detailed performance evaluation on a \CI3\ processor
    8282as our primary evaluation platform, addressing a
    8383number of microarchitectural issues including cache
  • docs/PACT2011/04-methodology.tex

    r1041 r1078  
    8989dewiki.xml XML files represent document-oriented XML inputs,
    9090containing three-byte and four-byte UTF8 sequence.  The remaining
    91 files are data-oriented inputs and consist of only ASCII
     91files are data-oriented inputs and consist of only ASCI3I
    9292characters. 
    9393
     
    115115\end{table}
    116116
    117 \paragraph {Intel \CI{}}
    118 The Intel \CI\ is a Nehalem based processor produced by Intel. The
     117\paragraph {Intel \CI3{}}
     118The Intel \CI3\ is a Nehalem based processor produced by Intel. The
    119119intent of this processor is to serve as an example low end server
    120120processor. Table \ref{i3info} gives the hardware description of the
    121 Intel \CI\ machine selected.
     121Intel \CI3\ machine selected.
    122122
    123123\begin{table}[h]
     
    136136\end{tabular}
    137137\end{center}
    138 \caption{\CI{}}
     138\caption{\CI3{}}
    139139\label{i3info}
    140140\end{table}
     
    143143The Intel Core i5 is a \SB\ based processor produced by
    144144Intel. Table \ref{sandybridgeinfo} gives the hardware description of the
    145 Intel \CI\ machine selected.
     145Intel \CI3\ machine selected.
    146146
    147147\begin{table}[h]
  • docs/PACT2011/05-corei3.tex

    r1048 r1078  
    1 \section{Baseline Evaluation on \CI{}}
     1\section{Baseline Evaluation on \CI3{}}
    22
    33%some of the numbers are roughly calculated, needs to be recalculated for final version
    44\subsection{Cache behavior}
    5 \CI\ has a three level cache hierarchy.  The miss penalty for each
     5\CI3\ has a three level cache hierarchy.  The miss penalty for each
    66level is approximately 4, 11, and 36 cycles respectively.  Figure
    77\ref{corei3_L1DM}, Figure \ref{corei3_L2DM} and Figure
     
    2222\includegraphics[width=0.5\textwidth]{plots/corei3_L1DM.pdf}
    2323\end{center}
    24 \caption{L1 Data Cache Misses on \CI\ (y-axis: Cache Misses per KByte)}
     24\caption{L1 Data Cache Misses on \CI3\ (y-axis: Cache Misses per KByte)}
    2525\label{corei3_L1DM}
    2626\end{figure}
     
    3030\includegraphics[width=0.5\textwidth]{plots/corei3_L2DM.pdf}
    3131\end{center}
    32 \caption{L2 Data Cache Misses on \CI\ (y-axis: Cache Misses per KByte)}
     32\caption{L2 Data Cache Misses on \CI3\ (y-axis: Cache Misses per KByte)}
    3333\label{corei3_L2DM}
    3434\end{figure}
     
    3838\includegraphics[width=0.5\textwidth]{plots/corei3_L3CM.pdf}
    3939\end{center}
    40 \caption{L3 Cache Misses on \CI\ (y-axis: Cache Misses per KByte)}
     40\caption{L3 Cache Misses on \CI3\ (y-axis: Cache Misses per KByte)}
    4141\label{corei3_L3TM}
    4242\end{figure}
     
    7070\includegraphics[width=0.5\textwidth]{plots/corei3_BR.pdf}
    7171\end{center}
    72 \caption{Branches on \CI\ (y-axis: Branches per KByte)}
     72\caption{Branches on \CI3\ (y-axis: Branches per KByte)}
    7373\label{corei3_BR}
    7474\end{figure}
     
    7878\includegraphics[width=0.5\textwidth]{plots/corei3_BM.pdf}
    7979\end{center}
    80 \caption{Branch Mispredictions on \CI\ (y-axis: Branch Mispredictions per KByte)}
     80\caption{Branch Mispredictions on \CI3\ (y-axis: Branch Mispredictions per KByte)}
    8181\label{corei3_BM}
    8282\end{figure}
     
    147147several cycles per byte.  However, transcoding using parallel
    148148bitstreams can be much faster and it takes less than a cycle per byte
    149 to transcode ASCII files such as road.gml, po.xml and soap.xml
     149to transcode ASCI3I files such as road.gml, po.xml and soap.xml
    150150\cite{Cameron2008}.
    151151
     
    154154\includegraphics[width=0.5\textwidth]{plots/corei3_TOT.pdf}
    155155\end{center}
    156 \caption{Processing Time on \CI\ (y-axis: Total CPU Cycles per KByte)}
     156\caption{Processing Time on \CI3\ (y-axis: Total CPU Cycles per KByte)}
    157157\label{corei3_TOT}
    158158\end{figure}
     
    163163have worked hard to develop power efficient chips. We studied the
    164164power and energy consumption of Parabix in comparison with Expat and
    165 Xerces on \CI{}. 
     165Xerces on \CI3{}. 
    166166 
    167167Figure \ref{corei3_power} shows the average power consumed by the four
    168 different parsers.  The average power of \CI{} 530 is about 21 watts.
     168different parsers.  The average power of \CI3{} 530 is about 21 watts.
    169169This model released by Intel last year has a good reputation for power
    170170efficiency.  Parabix2 dominated by SIMD instructions uses only about
     
    175175\includegraphics[width=0.5\textwidth]{plots/corei3_power.pdf}
    176176\end{center}
    177 \caption{Average Power on \CI\ (watts)}
     177\caption{Average Power on \CI3\ (watts)}
    178178\label{corei3_power}
    179179\end{figure}
     
    190190\includegraphics[width=0.5\textwidth]{plots/corei3_energy.pdf}
    191191\end{center}
    192 \caption{Energy Consumption on \CI\ ($\mu$J per KByte)}
     192\caption{Energy Consumption on \CI3\ ($\mu$J per KByte)}
    193193\label{corei3_energy}
    194194\end{figure}
  • docs/PACT2011/06-scalability.tex

    r1048 r1078  
    11\section{Scalability}
    22\subsection{Performance}
    3 Figure \ref{Scalability} (a) shows the performance of Parabix2 on three different cores: \CO{}, \CI\ and \SB{}.
     3Figure \ref{Scalability} (a) shows the performance of Parabix2 on three different cores: \CO{}, \CI3\ and \SB{}.
    44The average processing time of the five workloads, which is evaluated as CPU cycles per thousand bytes,
    55is divided up by bitstream parsing and byte space postprocessing.
    66Bitstream parsing, which mainly consists of SIMD instructions,
    7 is able to achieve 17\% performance improvement moving from \CO\ to \CI{};
    8 22\% performance improvement moving from \CI\ to \SB{},
     7is able to achieve 17\% performance improvement moving from \CO\ to \CI3{};
     822\% performance improvement moving from \CI3\ to \SB{},
    99which is relatively stable compared to postprocessing,
    10 which gains 18\% to 31\% performance moving from \CO\ to \CI{};
    11 0 to 17\% performance improvement moving from \CI\ to \SB{}.
     10which gains 18\% to 31\% performance moving from \CO\ to \CI3{};
     110 to 17\% performance improvement moving from \CI3\ to \SB{}.
    1212
    1313As comparison, we also measured the performance of Expat on all the three cores, which is shown is Figure \ref{Scalability} (b).
    14 The performance improvement is less than 5\% by running Expat on \CI\ instead of \CO\
    15 and it is less than 10\% by running on \SB\ instead of \CI{}.
     14The performance improvement is less than 5\% by running Expat on \CI3\ instead of \CO\
     15and it is less than 10\% by running on \SB\ instead of \CI3{}.
    1616
    1717Parabix2 scales much better than Expat and is able to achieve an overall performance improvement
     
    3535
    3636The newer processors are not only designed to have better performance but also more energy-efficient.
    37 Figure \ref{power_Parabix2} shows the average power when running Parabix2 on \CO{}, \CI\ and \SB\ with different input files.
    38 On \CO{}, the average power is about 32 watts. \CI\ saves 30\% of the power compared with \CO{}.
    39 \SB\ saves 25\% of the power compared with \CI\ and consumes only 15 watts.
     37Figure \ref{power_Parabix2} shows the average power when running Parabix2 on \CO{}, \CI3\ and \SB\ with different input files.
     38On \CO{}, the average power is about 32 watts. \CI3\ saves 30\% of the power compared with \CO{}.
     39\SB\ saves 25\% of the power compared with \CI3\ and consumes only 15 watts.
    4040
    4141The energy consumption is further improved by better performance, which means a shorter processing time, as we moved to the newer cores.
  • docs/PACT2011/main.tex

    r1039 r1078  
    1212\usepackage{amssymb}    % for \varnothing (empty set) symbol
    1313\def\lb{\linebreak[1]}
    14 \def\CI{Core-i3}
     14\def\CI3{Core-i3}
    1515\def\SB{SandyBridge}
    1616\def\CO{Core2}
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