Ignore:
Timestamp:
Apr 8, 2011, 2:31:22 PM (9 years ago)
Author:
ksherdy
Message:

Update macros \CI to \CI3

File:
1 edited

Legend:

Unmodified
Added
Removed
  • docs/PACT2011/05-corei3.tex

    r1048 r1078  
    1 \section{Baseline Evaluation on \CI{}}
     1\section{Baseline Evaluation on \CI3{}}
    22
    33%some of the numbers are roughly calculated, needs to be recalculated for final version
    44\subsection{Cache behavior}
    5 \CI\ has a three level cache hierarchy.  The miss penalty for each
     5\CI3\ has a three level cache hierarchy.  The miss penalty for each
    66level is approximately 4, 11, and 36 cycles respectively.  Figure
    77\ref{corei3_L1DM}, Figure \ref{corei3_L2DM} and Figure
     
    2222\includegraphics[width=0.5\textwidth]{plots/corei3_L1DM.pdf}
    2323\end{center}
    24 \caption{L1 Data Cache Misses on \CI\ (y-axis: Cache Misses per KByte)}
     24\caption{L1 Data Cache Misses on \CI3\ (y-axis: Cache Misses per KByte)}
    2525\label{corei3_L1DM}
    2626\end{figure}
     
    3030\includegraphics[width=0.5\textwidth]{plots/corei3_L2DM.pdf}
    3131\end{center}
    32 \caption{L2 Data Cache Misses on \CI\ (y-axis: Cache Misses per KByte)}
     32\caption{L2 Data Cache Misses on \CI3\ (y-axis: Cache Misses per KByte)}
    3333\label{corei3_L2DM}
    3434\end{figure}
     
    3838\includegraphics[width=0.5\textwidth]{plots/corei3_L3CM.pdf}
    3939\end{center}
    40 \caption{L3 Cache Misses on \CI\ (y-axis: Cache Misses per KByte)}
     40\caption{L3 Cache Misses on \CI3\ (y-axis: Cache Misses per KByte)}
    4141\label{corei3_L3TM}
    4242\end{figure}
     
    7070\includegraphics[width=0.5\textwidth]{plots/corei3_BR.pdf}
    7171\end{center}
    72 \caption{Branches on \CI\ (y-axis: Branches per KByte)}
     72\caption{Branches on \CI3\ (y-axis: Branches per KByte)}
    7373\label{corei3_BR}
    7474\end{figure}
     
    7878\includegraphics[width=0.5\textwidth]{plots/corei3_BM.pdf}
    7979\end{center}
    80 \caption{Branch Mispredictions on \CI\ (y-axis: Branch Mispredictions per KByte)}
     80\caption{Branch Mispredictions on \CI3\ (y-axis: Branch Mispredictions per KByte)}
    8181\label{corei3_BM}
    8282\end{figure}
     
    147147several cycles per byte.  However, transcoding using parallel
    148148bitstreams can be much faster and it takes less than a cycle per byte
    149 to transcode ASCII files such as road.gml, po.xml and soap.xml
     149to transcode ASCI3I files such as road.gml, po.xml and soap.xml
    150150\cite{Cameron2008}.
    151151
     
    154154\includegraphics[width=0.5\textwidth]{plots/corei3_TOT.pdf}
    155155\end{center}
    156 \caption{Processing Time on \CI\ (y-axis: Total CPU Cycles per KByte)}
     156\caption{Processing Time on \CI3\ (y-axis: Total CPU Cycles per KByte)}
    157157\label{corei3_TOT}
    158158\end{figure}
     
    163163have worked hard to develop power efficient chips. We studied the
    164164power and energy consumption of Parabix in comparison with Expat and
    165 Xerces on \CI{}. 
     165Xerces on \CI3{}. 
    166166 
    167167Figure \ref{corei3_power} shows the average power consumed by the four
    168 different parsers.  The average power of \CI{} 530 is about 21 watts.
     168different parsers.  The average power of \CI3{} 530 is about 21 watts.
    169169This model released by Intel last year has a good reputation for power
    170170efficiency.  Parabix2 dominated by SIMD instructions uses only about
     
    175175\includegraphics[width=0.5\textwidth]{plots/corei3_power.pdf}
    176176\end{center}
    177 \caption{Average Power on \CI\ (watts)}
     177\caption{Average Power on \CI3\ (watts)}
    178178\label{corei3_power}
    179179\end{figure}
     
    190190\includegraphics[width=0.5\textwidth]{plots/corei3_energy.pdf}
    191191\end{center}
    192 \caption{Energy Consumption on \CI\ ($\mu$J per KByte)}
     192\caption{Energy Consumption on \CI3\ ($\mu$J per KByte)}
    193193\label{corei3_energy}
    194194\end{figure}
Note: See TracChangeset for help on using the changeset viewer.