# Changeset 1349 for docs/HPCA2012/01-intro.tex

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Timestamp:
Aug 23, 2011, 9:55:22 AM (8 years ago)
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Minor edits in abstract/intro

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 r1348 shut off. Chip makers strive to achieve energy efficient computing by operating at more optimal core frequencies and aim to increase performance with larger number of cores. Unfortunately, given the performance with a larger number of cores. Unfortunately, given the limited levels of parallelism that can be found in applications~\cite{blake-isca-2010}, it is not certain how many cores transposing byte-oriented character data into parallel bit streams for the individual bits of each byte, the Parabix framework exploits the SIMD extensions (SSE/AVX on x86, Neon on ARM) on commodity processors SIMD extensions on commodity processors (SSE/AVX on x86, Neon on ARM) to process hundreds of character positions in an input stream simultaneously.  To achieve transposition, Parabix exploits sophisticated SIMD instructions that enable data elements to be packed and unpacked from registers in a regular manner which improve the and unpacked from registers in a regular manner which improves the overall cache access behavior of the application resulting in significantly fewer misses and better utilization.  Parabix also applications ranging from Office Open XML in Microsoft Office to NDFD XML of the NOAA National Weather Service, from KML in Google Earth to Castor XML in the Martian Rovers, a XML data in Android phones.  XML Castor XML in the Martian Rovers, as well as ubiquitous XML data in Android phones.  XML parsing efficiency is important for multiple application areas; in server workloads the key focus in on overall transactions per second, while in applications in the network switches and cell phones, latency and the energy are of paramount importance.  Traditional software-based XML parsers have many inefficiencies due to complex input-dependent branching structures leading to considerable branch misprediction penalties as well as poor use of memory bandwidth and while in applications in network switches and cell phones, latency and energy are of paramount importance.  Traditional software-based XML parsers have many inefficiencies including considerable branch misprediction penalties due to complex input-dependent branching structures as well as poor use of memory bandwidth and data caches due to byte-at-a-time processing and multiple buffering. XML ASIC chips have been around for over 6 years, but typically lag behind CPUs in technology due to cost constraints. Our focus is how much can we improve performance of the XML parser on commodity much we can improve performance of the XML parser on commodity processors with Parabix technology. In the end, as summarized by Figure~\ref{perf-energy} our Parabix-based XML parser improves the performance by ?$\times$ and energy efficiency by ?$\times$ compared performance by %?$\times$ and energy efficiency %by ?$\times$ several-fold compared to widely-used software parsers and approaching the performance of ?$cycles/input-byte$ performance of ASIC XML parsers~\cite{}.\footnote{The actual energy consumption of the XML %?$cycles/input-byte$ performance of ASIC XML parsers.%~\cite{}. \footnote{The actual energy consumption of the XML ASIC chips is not published by the companies.}