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Timestamp:
Aug 31, 2011, 6:14:20 PM (8 years ago)
Author:
ashriram
Message:

spell checked evaluation

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1 edited

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  • docs/HPCA2012/10-related.tex

    r1407 r1411  
    1515of numerous multi-threaded and hardware-based approaches:
    1616Multithreaded XML techniques include preparsing the XML file to locate
    17 key partitioning points \cite{ZhangPanChiu09} and speculative p-DFAs
    18 \cite{ZhangPanChiu09}. Hardware methods include custom XML chips
    19 \cite{Leventhal2009} and FPGA-based implementations
    20 \cite{DaiNiZhu2010}.  Recently Cameron et
    21 al.~\cite{CameronHerdyLin2008, cameron-EuroPar2011} accelerated XML
    22 parsing using SSE instructions. Finally, other have explored the
    23 design of custom hardware for bit parallel operations in network
     17key partitioning points~\cite{ParaDOM2009,LiWangLiuLi2009} and
     18speculative p-DFAs~\cite{ZhangPanChiu09}. Hardware methods include
     19custom XML chips \cite{Leventhal2009} and FPGA-based implementations
     20\cite{DaiNiZhu2010}.  Intel's SSE4 instructions targeted
     21XML parsers, but these have not seen widespread use because of portability
     22concerns and the programming challenges that accompany low level
     23instructions~\cite{sse4}. Recently, Cameron et
     24al.~\cite{CameronHerdyLin2008, cameron-EuroPar2011} designed an
     25accelerated XML parser using widely available SSE2
     26instructions. Finally, others have explored the design of custom
     27hardware for bit parallel operations for text search in network
    2428processors~\cite{tan-sherwood-isca-2005}.
     29
     30
     31
     32% To accelerate XML parsingmost of the recent work has
     33% focused on parallelization through the use of multicore parallelism
     34% for chip multiprocessors \cite{ZhangPanChiu09, },
     35
     36
     37
    2538
    2639
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