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Timestamp:
Dec 13, 2011, 4:50:42 PM (8 years ago)
Author:
lindanl
Message:

minor changes

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  • docs/HPCA2012/final_ieee/04-methodology.tex

    r1743 r1774  
    66against two widely available open-source parsers: Xerces-C \cite{xerces} and Expat \cite{expat}.
    77Each of the parsers is evaluated on the task of implementing the
    8 parsing and well-formedness validation requirements of the full
     8parsing and well-formedness checking requirements of the full
    99XML 1.0 specification\cite{TR:XML}.
    1010Xerces-C version 3.1.1 (SAX) is a validating XML
     
    7272
    7373\paragraph{Platform Hardware:}
    74 SSE extensions have been available on commodity Intel processors for
     74SSE SIMD extensions have been available on commodity Intel processors for
    7575over a decade since the Pentium III. They have steadily evolved with
    7676improvements in instruction latency, cache interface, register
    7777resources, and the addition of domain specific instructions. Here we
    7878investigate SIMD extensions across three different generations of
    79 intel processors (hardware details in Table \ref{hwinfo}). We compare
    80 the energy and performance profile of the Parabix under the platforms.
     79intel processors (hardware details given in Table \ref{hwinfo}). We compare
     80the energy and performance profile of the Parabix parser on each of the platforms.
    8181We also analyze the implementation specifics of SIMD extensions under
    82 various microarchitectures and the newer AVX extensions supported by
    83 Sandybridge.
     82various microarchitectures as well as the newer AVX extensions supported by \SB{}.
    8483
    8584
    86 We investigated the execution profiles of each XML parser
     85We investigate the execution profiles of each XML parser
    8786using the performance counters found in the processor.
    88 We chose several key hardware events that provide insight into the profile of each
     87We choose several key hardware events that provide insight into the profile of each
    8988application and indicate if the processor is doing useful work
    9089~\cite{bellosa2001, bertran2010}. 
    91 The set of events included in our study are: Branch instructions, Branch mispredictions,
    92 Integer instructions, SIMD instructions, and Cache misses. In
     90The set of events included in our study are: branch instructions, branch mispredictions,
     91integer instructions, SIMD instructions, and cache misses. In
    9392addition, we characterize the SIMD operations and study the type and
    9493class of SIMD operations using the Intel Pin binary instrumentation
     
    108107monitored by an Agilent 34410a digital multimeter at the granularity
    109108of 100 samples per second. This measurement captures the instantaneous
    110 power to the processor package, including cores, caches, northbridge
     109power to the processor package, including the cores, caches, northbridge
    111110memory controller, and the quick-path interconnects. We obtain samples
    112111throughout the entire execution of the program and then calculate overall
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