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Timestamp:
Dec 14, 2011, 2:27:41 PM (8 years ago)
Author:
ashriram
Message:

Final pass

Location:
docs/HPCA2012/final_ieee
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14 edited

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  • docs/HPCA2012/final_ieee/01-intro.tex

    r1779 r1783  
    6262
    6363
    64 \begin{figure}
    65 \begin{center}
    66 \includegraphics[width=85mm]{plots/performance_energy_chart.pdf}
    67 \end{center}
    68 \caption{XML Parser Technology Energy vs. Performance}
    69 \label{perf-energy}
    70 \end{figure}
    7164
    72 
     65%\pagebreak
    7366In this paper, we generalize parallel bit streams and develop the
    7467Parabix programming framework to help programmers build text
     
    8477commodity multicores.
    8578
     79\pagebreak
    8680We study in detail the performance of Parabix technology
    8781in application to the problem of XML parsing on multiple
     
    9589wasted on cache misses and data transfers.\footnote{The actual energy consumption of the XML
    9690  ASIC chips is not published by the companies.}
     91
     92
     93\begin{figure}[!h]
     94\begin{center}
     95\includegraphics[trim = 2mm 1mm 1mm 2mm, clip, width=85mm]{plots/performance_energy_chart.pdf}
     96\end{center}
     97\caption{XML Parser Technology Energy vs. Performance}
     98\label{perf-energy}
     99\end{figure}
    97100
    98101We make the following contributions:
     
    145148
    146149
     150
  • docs/HPCA2012/final_ieee/02-background.tex

    r1774 r1783  
    3535
    3636
    37 \subsection{XML}
    3837% In 1998, the W3C officially adopted XML as a standard for data interchange.
    3938% Today, XML can be found everywhere from mobile websites and cloud computing to server-side database engines.
     
    4847
    4948\begin{figure}[h]
    50 
     49\vspace{-15pt}
    5150{\footnotesize
    5251\begin{center}
  • docs/HPCA2012/final_ieee/03-research.tex

    r1775 r1783  
    4949\label{fig:BitStreamsExample}
    5050\end{figure}
     51\pagebreak
    5152
    5253The advantage of the parallel bit stream representation is that we can
    5354use the 128-bit SIMD registers commonly found on commodity processors
    5455(e.g. SSE on Intel) to process 128 byte positions at a time using
    55 bitwise logical, shift and arithmetic operations.
    56 
    57 Just as forward and inverse Fourier transforms are used to transform
    58 between the time and frequency domains in signal processing, bit
    59 stream transposition and inverse transposition provides ``byte space''
    60 and ``bit space'' domains for text.  The goal of the Parabix framework is
    61 to support efficient text processing using these two equivalent
    62 representations in the analogous way that efficient signal processing
    63 benefits from the use of the frequency domain in some cases and the
    64 time domain in others.
     56bitwise logical, shift and arithmetic operations. Just as forward and
     57inverse Fourier transforms are used to transform between the time and
     58frequency domains in signal processing, bit stream transposition and
     59inverse transposition provides ``byte space'' and ``bit space''
     60domains for text.  The Parabix framework supports
     61efficient text processing using these two equivalent representations
     62analogous to signal processing that benefits from the use of the
     63frequency domain and time domain.
    6564
    6665In the Parabix framework, basis bit streams are used as the starting
     
    122121important observation here is that a range of characters can sometimes
    123122take fewer operations and require fewer basis bit streams to compute
    124 than individual characters.  Finding optimal solutions to all
    125 character-classes is non-trivial and goes beyond the scope of this
     123than individual characters.  Finding optimal solutions for all
     124character-classes is beyond the scope of this
    126125paper.
    127126
     
    281280\end{figure}
    282281
    283 
     282\pagebreak
    284283The Pablo compiler abstracts away the details of
    285284programming parallel bit stream code in terms of finite
  • docs/HPCA2012/final_ieee/04-methodology.tex

    r1774 r1783  
     1\pagebreak
    12\section{Evaluation Framework}
    23\label{section:methodology}
     
    4950\end{table}
    5051
    51 \begin{table}[htbp]
    52 {
    53   \footnotesize
    54   \begin{center}
    55 {
    56 \begin{tabular}{|l||@{~}l@{~}|@{~}l@{~}|@{~}l@{~}|}
    57 \hline
    58 Processor & Core2 Duo & i3-530 & Sandybridge\\ \hline
    59 Frequency &  2.13GHz & 2.93GHz & 2.80GHz \\ \hline
    60 L1 D Cache & 32KB & 32KB & 32KB \\ \hline       
    61 L2 Cache & Shared 2MB & 256KB/core & 256KB/core \\ \hline
    62 L3 Cache & --- & 4MB  & 6MB \\ \hline
    63 Max TDP & 65W & 73W &  95W \\ \hline
    64 \end{tabular}
    65 }
    66 \end{center}
    67   }
    68 \caption{Platform Hardware Specs}
    69 \label{hwinfo}
    70 \end{table}
     52%\begin{table}[htbp]
     53%{
     54%  \footnotesize
     55%  \begin{center}
     56%{
     57%\begin{tabular}{|l||@{~}l@{~}|@{~}l@{~}|@{~}l@{~}|}
     58%\hline
     59%Processor & Core2 Duo & i3-530 & Sandybridge\\ \hline
     60%Frequency &  2.13GHz & 2.93GHz & 2.80GHz \\ \hline
     61%L1 D Cache & 32KB & 32KB & 32KB \\ \hline     
     62%L2 Cache & Shared 2MB & 256KB/core & 256KB/core \\ \hline
     63%L3 Cache & --- & 4MB  & 6MB \\ \hline
     64%Max TDP & 65W & 73W &  95W \\ \hline
     65%\end{tabular}
     66%}
     67%\end{center}
     68%  }
     69%\caption{Platform Hardware Specs}
     70%\label{hwinfo}
     71%\end{table}
    7172
    7273
    7374\paragraph{Platform Hardware:}
    74 SSE SIMD extensions have been available on commodity Intel processors for
    75 over a decade since the Pentium III. They have steadily evolved with
    76 improvements in instruction latency, cache interface, register
     75SSE SIMD extensions have been available on commodity Intel processors
     76for over a decade since the Pentium III. They have steadily evolved
     77with improvements in instruction latency, cache interface, register
    7778resources, and the addition of domain specific instructions. Here we
    7879investigate SIMD extensions across three different generations of
    79 intel processors (hardware details given in Table \ref{hwinfo}). We compare
    80 the energy and performance profile of the Parabix parser on each of the platforms.
    81 We also analyze the implementation specifics of SIMD extensions under
    82 various microarchitectures as well as the newer AVX extensions supported by \SB{}.
    83 
    84 
    85 We investigate the execution profiles of each XML parser
    86 using the performance counters found in the processor.
    87 We choose several key hardware events that provide insight into the profile of each
    88 application and indicate if the processor is doing useful work
    89 ~\cite{bellosa2001, bertran2010}. 
    90 The set of events included in our study are: branch instructions, branch mispredictions,
    91 integer instructions, SIMD instructions, and cache misses. In
    92 addition, we characterize the SIMD operations and study the type and
    93 class of SIMD operations using the Intel Pin binary instrumentation
     80intel processors: Core2Duo (2.13Ghz,32KB L1, 2MB Shared L2), Core i3
     81(2.9Ghz, 32KB L1,256KB L2, 4MB Shared LLC), and Sandybridge (2.8Ghz,
     8232KB L1, 256KB L2, 6MB LLC). We compare the energy and performance
     83profile of the Parabix under the platforms.  We also analyze the
     84implementation specifics of SIMD extensions under various
     85microarchitectures and the newer AVX extensions.  We investigate the
     86execution profiles of each XML parser using the performance counters
     87found in the processor.  We choose several key hardware events that
     88provide insight into the profile of each application and indicate if
     89the processor is doing useful work ~\cite{bellosa2001, bertran2010}.
     90The set of events included in our study are: branch instructions,
     91branch mispredictions, integer instructions, SIMD instructions, and
     92cache misses. In addition, we characterize the SIMD operations and
     93study the type and class of SIMD operations using the Intel Pin
    9494framework.
    9595
     
    9898
    9999\paragraph{Energy Measurement:}
    100 A key benefit of the Parabix parser is its more efficient use of the
    101 processor pipeline which reflects in the overall energy usage.  We
    102 measure the energy consumption of the processor directly using a
     100%A key benefit of the
     101We measure the energy consumption of the processor directly using a
    103102current clamp. We apply the Fluke i410 current clamp \cite{clamp} to the 12V wires
    104103that supply power to the processor sockets. The clamp detects the
     
    111110throughout the entire execution of the program and then calculate overall
    112111total energy as  $12V*\sum^{N_{samples}}_{i=1} Sample_i$.
    113 
    114 
  • docs/HPCA2012/final_ieee/05-corei3.tex

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    1 \section{Efficiency of the Parabix-XML Parser}
     1\section{Efficiency of Parabix-XML}
    22\label{section:baseline}
    33In this section we analyze the energy and performance characteristics
     
    189189
    190190
    191  The energy trends shown in Figure \ref{corei3_energy} reveal an
    192  interesting result. Parabix consumes substantially less energy than
    193  the other parsers. Parabix consumes 50 to 75 nJ per byte while Expat
    194  and Xerces consume 80nJ to 320nJ and 140nJ to 370nJ per byte
    195  respectively. Parabix-XML experiences minimal increase in power consumption
    196  ($\sim5\%$) as compared to the conventional parsers. While the SIMD
    197  functional units are significantly wider than the scalar
    198  counterparts, register width and functional unit power account only
    199  for a small fraction of the overall power consumption in a pipeline
    200  processor. Parabix amortizes the fetch and data access overheads over
    201  multiple data parallel operations. Although Parabix requires
    202  slightly more power (per instruction), the processing time of Parabix
    203  is significantly lower resulting in an overall improvement in energy.
    204 
    205 
    206 
     191Parabix consumes substantially less energy (see
     192Figure \ref{corei3_energy} ) than
     193the other parsers. Parabix consumes 50 to 75 nJ per byte while Expat
     194and Xerces consume 80nJ to 320nJ and 140nJ to 370nJ per byte
     195respectively. Parabix-XML experiences minimal increase in power
     196consumption ($\sim5\%$) as compared to the conventional parsers. While
     197the SIMD functional units are significantly wider than the scalar
     198counterparts, register width and functional unit power account only
     199for a small fraction of the overall power consumption in a pipeline
     200processor. Parabix amortizes the fetch and data access overheads over
     201multiple data parallel operations. Although Parabix requires slightly
     202more power (per instruction), the processing time of Parabix is
     203significantly lower resulting in an overall improvement in energy.
     204The Parabix parser makes efficient use of the processor pipeline which
     205minimizes overall energy wastage.
     206
     207
     208
     209
  • docs/HPCA2012/final_ieee/06-scalability.tex

    r1775 r1783  
    122122\begin{figure*}[!htbp]
    123123\begin{center}
    124 \includegraphics[height=0.25\textheight]{plots/InsMix.pdf}
     124\includegraphics[trim = 2mm 1mm 1mm 2mm, clip, height=0.25\textheight]{plots/InsMix.pdf}
    125125\end{center}
    126126\caption{Parabix Instruction Counts (y-axis: Instructions per kB)}
  • docs/HPCA2012/final_ieee/07-avx.tex

    r1778 r1783  
    6363
    6464
    65 Note that, in each workload, the number of non-SIMD instructions
    66 remains relatively constant with each implementation.  As expected,
    67 the number of bitwise SIMD operations remains the same
    68 for both SSE and 128-bit AVX while dropping dramatically when operating
    69 256-bits at a time. The reduction was measured at 32\%--39\% depending
    70 on markup density of the workload. The ``other SIMD'' class
    71 shows a substantial 30\%--35\% reduction with AVX 128-bit technology
    72 compared to SSE. This reduction is due to elimination of register
    73 unloading and reloading when SIMD operations are compiled using
    74 3-operand AVX form versus 2-operand SSE form.  A further 10\%--20\%
    75 reduction is also observed when Parabix-XML utilized the AVX runtime
    76 library.
     65The number of non-SIMD instructions remains relatively constant with
     66each implementation.  The number of bitwise SIMD
     67operations remains the same for both SSE and 128-bit AVX while
     68dropping dramatically when operating 256-bits at a time. The reduction
     69was measured at 32\%--39\% depending on markup density of the
     70workload. The ``other SIMD'' class shows a substantial 30\%--35\%
     71reduction with AVX 128-bit technology compared to SSE. This reduction
     72is due to elimination of register unloading and reloading when SIMD
     73operations are compiled using 3-operand AVX form versus 2-operand SSE
     74form.  A further 10\%--20\% reduction is also observed when
     75Parabix-XML utilized the AVX runtime library.
    7776
    7877
    7978%[AS] Check numbers.
    80 The reductions in instruction counts are quite dramatic with the AVX
    81 extensions in Parabix demonstrating the ability of our runtime
    82 framework to exploit the available hardware resources. As shown in
    83 Figure \ref{avx}, the benefits of the reduced SIMD instruction count
    84 are achieved only in the AVX 128-bit version.  In this case, the
    85 benefits of 3-operand form seem to fully translate to performance
    86 benefits.  Based on the reduction of overall Bitwise-SIMD instructions
    87 we expected a 11\% improvement in performance. 
    88 Surprisingly, the performance of Parabix in the 256-bit AVX
    89 implementation does not improve significantly and actually degrades
    90 for files with higher markup density ($\sim11\%$). dew.xml, on
    91 which bitwise-SIMD instructions were reduced by 39\%, saw a performance
    92 improvement of 8\%.  We believe that this is primarily due to the
    93 intricacies of the first generation AVX implementation in \SB{}, with
    94 significant latency in many of the 256-bit instructions in comparison
    95 to their 128-bit counterparts. The 256-bit instructions also have
    96 different scheduling constraints that seem to reduce overall
    97 throughput.  If these latency issues can be addressed in future AVX
    98 implementations, further performance and energy benefits
    99 could be realized in Parabix-XML.
     79The reductions in instruction counts are significant with the AVX
     80extensions demonstrating the ability of Parabix to
     81exploit wider SIMD extensions. Figure
     82\ref{avx} shows the benefits of the reduced SIMD instruction count are
     83achieved only in the AVX 128-bit version; The 3-operand form seems to fully translate to performance benefits.
     84Based on the reduction of overall Bitwise-SIMD instructions we
     85expected a 11\% improvement in performance.  Surprisingly, the
     86performance of Parabix in the 256-bit AVX implementation does not
     87improve significantly and actually degrades for files with higher
     88markup density ($\sim11\%$). dew.xml, on which bitwise-SIMD
     89instructions were reduced by 39\%, saw a performance improvement of
     908\%.  We believe that this is primarily due to the intricacies of the
     91first generation AVX implementation in \SB{}, with significant latency
     92in many of the 256-bit instructions in comparison to their 128-bit
     93counterparts. The 256-bit instructions also have different scheduling
     94constraints that seem to reduce overall throughput.  If these latency
     95issues can be addressed in future AVX implementations, further
     96performance and energy benefits could be realized by Parabix.
    10097
    10198
  • docs/HPCA2012/final_ieee/09-pipeline.tex

    r1774 r1783  
    1010energy costs. Parabix-XML can improve performance and reduce energy consumption
    1111by improving the overall computation efficiency.
    12 However, up to this point, we restricted Parabix-XML to a
    13 single core. In this section, we discuss our parallelized version of Parabix-XML
     12 In this section, we discuss our parallelized version of Parabix-XML
    1413to study the effects of thread-level parallelism in
    1514conjunction with Parabix-XML's data parallelism.
     
    4847neither speculation nor pre-parsing.
    4948As described in Section~\ref{section:parser}, Parabix-XML consists of multiple
    50 passes that, on every chunk of input data, interact with each other
     49passes that operate on every chunk of input data, and interact with each other
    5150in sequence with no data movement from later to earlier
    5251passes. This fits well into the mold of pipeline parallelism. We
  • docs/HPCA2012/final_ieee/final.aux

    r1780 r1783  
    66\citation{cameron-EuroPar2011}
    77\@writefile{toc}{\contentsline {section}{\numberline {1}Introduction}{1}}
    8 \@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces XML Parser Technology Energy vs. Performance\relax }}{1}}
    9 \providecommand*\caption@xref[2]{\@setref\relax\@undefined{#1}}
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    118\citation{TR:XML}
    129\citation{xerces}
     10\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces XML Parser Technology Energy vs. Performance\relax }}{2}}
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    1313\@writefile{toc}{\contentsline {section}{\numberline {2}Background}{2}}
    1414\newlabel{section:background}{{2}{2}}
    15 \@writefile{toc}{\contentsline {subsection}{\numberline {2.1}XML}{2}}
    1615\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces Sample XML Document\relax }}{2}}
    1716\newlabel{fig:sample_xml}{{2}{2}}
    18 \@writefile{toc}{\contentsline {subsection}{\numberline {2.2}XML Parsers}{2}}
     17\@writefile{toc}{\contentsline {subsection}{\numberline {2.1}XML Parsers}{2}}
    1918\@writefile{toc}{\contentsline {section}{\numberline {3}The Parabix Framework}{3}}
    2019\newlabel{section:parabix}{{3}{3}}
     
    3029\@writefile{lof}{\contentsline {figure}{\numberline {6}{\ignorespaces Parallel Block Compiler (Pablo) Input/Output\relax }}{4}}
    3130\newlabel{fig:Pablo}{{6}{4}}
     31\@writefile{toc}{\contentsline {subsection}{\numberline {3.3}Parabix Runtime Libraries}{5}}
     32\@writefile{toc}{\contentsline {section}{\numberline {4}The Parabix XML Parser}{5}}
     33\newlabel{section:parser}{{4}{5}}
    3234\citation{xerces}
    3335\citation{expat}
    3436\citation{TR:XML}
    35 \@writefile{toc}{\contentsline {subsection}{\numberline {3.3}Parabix Runtime Libraries}{5}}
    36 \@writefile{toc}{\contentsline {section}{\numberline {4}The Parabix XML Parser}{5}}
    37 \newlabel{section:parser}{{4}{5}}
    38 \@writefile{toc}{\contentsline {section}{\numberline {5}Evaluation Framework}{5}}
    39 \newlabel{section:methodology}{{5}{5}}
    40 \newlabel{parsers}{{5}{5}}
    41 \@writefile{toc}{\contentsline {paragraph}{XML Parsers:}{5}}
    4237\citation{bellosa2001,bertran2010}
    4338\citation{clamp}
    4439\@writefile{lof}{\contentsline {figure}{\numberline {7}{\ignorespaces Parabix XML Parser Structure\relax }}{6}}
    4540\newlabel{parabix_arch}{{7}{6}}
     41\@writefile{toc}{\contentsline {section}{\numberline {5}Evaluation Framework}{6}}
     42\newlabel{section:methodology}{{5}{6}}
     43\newlabel{parsers}{{5}{6}}
     44\@writefile{toc}{\contentsline {paragraph}{XML Parsers:}{6}}
    4645\newlabel{workloads}{{5}{6}}
    4746\@writefile{toc}{\contentsline {paragraph}{XML Workloads:}{6}}
    4847\@writefile{lot}{\contentsline {table}{\numberline {1}{\ignorespaces XML Document Characteristics\relax }}{6}}
    4948\newlabel{XMLDocChars}{{1}{6}}
    50 \@writefile{lot}{\contentsline {table}{\numberline {2}{\ignorespaces Platform Hardware Specs\relax }}{6}}
    51 \newlabel{hwinfo}{{2}{6}}
    5249\@writefile{toc}{\contentsline {paragraph}{Platform Hardware:}{6}}
    5350\@writefile{toc}{\contentsline {paragraph}{Energy Measurement:}{6}}
    54 \@writefile{toc}{\contentsline {section}{\numberline {6}Efficiency of the Parabix-XML Parser}{6}}
     51\@writefile{toc}{\contentsline {section}{\numberline {6}Efficiency of Parabix-XML}{6}}
    5552\newlabel{section:baseline}{{6}{6}}
    56 \@writefile{toc}{\contentsline {subsection}{\numberline {6.1}Cache behavior}{6}}
    57 \@writefile{lot}{\contentsline {table}{\numberline {3}{\ignorespaces Cache Misses per kB of input data\relax }}{7}}
    58 \newlabel{cache_misses}{{3}{7}}
     53\@writefile{toc}{\contentsline {subsection}{\numberline {6.1}Cache behavior}{7}}
     54\@writefile{lot}{\contentsline {table}{\numberline {2}{\ignorespaces Cache Misses per kB of input data\relax }}{7}}
     55\newlabel{cache_misses}{{2}{7}}
    5956\@writefile{toc}{\contentsline {subsection}{\numberline {6.2}Branch Mispredictions}{7}}
    6057\newlabel{section:XML-branches}{{6.2}{7}}
     
    6259\newlabel{corei3_BM}{{8}{7}}
    6360\@writefile{toc}{\contentsline {subsection}{\numberline {6.3}SIMD Instructions vs. Total Instructions}{7}}
    64 \@writefile{lot}{\contentsline {table}{\numberline {4}{\ignorespaces SIMD Instruction Percentage\relax }}{7}}
    65 \newlabel{corei3_INS_p2}{{4}{7}}
     61\@writefile{lot}{\contentsline {table}{\numberline {3}{\ignorespaces SIMD Instruction Percentage\relax }}{7}}
     62\newlabel{corei3_INS_p2}{{3}{7}}
    6663\@writefile{toc}{\contentsline {subsection}{\numberline {6.4}Performance and Energy Characteristics}{7}}
    6764\newlabel{corei3_TOT}{{9(a)}{8}}
     
    9996\@writefile{lof}{\contentsline {figure}{\numberline {12}{\ignorespaces Parabix Instruction Counts (y-axis: Instructions per kB)\relax }}{10}}
    10097\newlabel{insmix}{{12}{10}}
     98\@writefile{lof}{\contentsline {figure}{\numberline {13}{\ignorespaces Parabix Performance (y-axis: ns per kB)\relax }}{10}}
     99\newlabel{avx}{{13}{10}}
    101100\@writefile{toc}{\contentsline {section}{\numberline {9}Multithreaded Parabix}{10}}
    102101\newlabel{section:multithread}{{9}{10}}
    103 \@writefile{lof}{\contentsline {figure}{\numberline {13}{\ignorespaces Parabix Performance (y-axis: ns per kB)\relax }}{10}}
    104 \newlabel{avx}{{13}{10}}
    105 \@writefile{lot}{\contentsline {table}{\numberline {5}{\ignorespaces Stage Division\relax }}{10}}
    106 \newlabel{pass_structure}{{5}{10}}
    107102\citation{DaiNiZhu2010}
    108103\citation{NicolaJohn03}
     
    118113\citation{CameronLin2009}
    119114\citation{cameron-EuroPar2011}
     115\@writefile{lot}{\contentsline {table}{\numberline {4}{\ignorespaces Stage Division\relax }}{11}}
     116\newlabel{pass_structure}{{4}{11}}
    120117\@writefile{toc}{\contentsline {section}{\numberline {10}Related Work}{11}}
    121118\newlabel{section:related}{{10}{11}}
    122119\@writefile{lof}{\contentsline {figure}{\numberline {14}{\ignorespaces Average Statistic of Multithreaded Parabix\relax }}{11}}
    123120\newlabel{multithread_perf}{{14}{11}}
    124 \@writefile{toc}{\contentsline {section}{\numberline {11}Conclusion}{11}}
    125 \newlabel{section:conclusion}{{11}{11}}
    126121\bibstyle{ieee/latex8}
    127122\bibdata{reference}
     
    149144\bibcite{tan-sherwood-isca-2005}{22}
    150145\bibcite{ZhangPanChiu09}{23}
     146\@writefile{toc}{\contentsline {section}{\numberline {11}Conclusion}{12}}
     147\newlabel{section:conclusion}{{11}{12}}
  • docs/HPCA2012/final_ieee/final.bbl

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    22
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    4 K.~Asanovic, R.~Bodik, B.~C. Catanzaro, J.~J. Gebis, P.~Husbands, K.~Keutzer,
    5   D.~A. Patterson, W.~L. Plishker, J.~Shalf, S.~W. Williams, and K.~A. Yelick.
     4K.~Asanovic, R.~Bodik, B.~C. Catanzaro, et al.
    65\newblock The landscape of parallel computing research: A view from {Berkeley}.
    76\newblock Technical Report UCB/EECS-2006-183, EECS Department, University of
     
    1817\newblock Decomposable and responsive power models for multicore processors
    1918  using performance counters.
    20 \newblock In {\em Proceedings of the 24th {ACM} International Conference on
    21   Supercomputing}, ICS '10, pages 147--158, New York, NY, USA, 2010. ACM.
     19\newblock In {\em Proc. of the 24th {ACM} Int'l. Conference on
     20  Supercomputing}, ICS '10, pages 147--158, ACM.
    2221
    2322\bibitem{TR:XML}
     
    3029\newblock A case study in {SIMD} text processing with parallel bit streams:
    3130  {UTF-8 to UTF-16} transcoding.
    32 \newblock In {\em Proceedings of the 13th {ACM SIGPLAN} Symposium on Principles
    33   and Practice of Parallel Programming}, PPoPP '08, pages 91--98, New York, NY,
    34   USA, 2008. ACM.
     31\newblock In {\em Proc. of the 13th {ACM SIGPLAN} Symposium on Principles
     32  and Practice of Parallel Programming}, PPoPP '08, pages 91--98, 2008. ACM.
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