Ignore:
Timestamp:
Dec 14, 2011, 2:27:41 PM (8 years ago)
Author:
ashriram
Message:

Final pass

File:
1 edited

Legend:

Unmodified
Added
Removed
  • docs/HPCA2012/final_ieee/04-methodology.tex

    r1774 r1783  
     1\pagebreak
    12\section{Evaluation Framework}
    23\label{section:methodology}
     
    4950\end{table}
    5051
    51 \begin{table}[htbp]
    52 {
    53   \footnotesize
    54   \begin{center}
    55 {
    56 \begin{tabular}{|l||@{~}l@{~}|@{~}l@{~}|@{~}l@{~}|}
    57 \hline
    58 Processor & Core2 Duo & i3-530 & Sandybridge\\ \hline
    59 Frequency &  2.13GHz & 2.93GHz & 2.80GHz \\ \hline
    60 L1 D Cache & 32KB & 32KB & 32KB \\ \hline       
    61 L2 Cache & Shared 2MB & 256KB/core & 256KB/core \\ \hline
    62 L3 Cache & --- & 4MB  & 6MB \\ \hline
    63 Max TDP & 65W & 73W &  95W \\ \hline
    64 \end{tabular}
    65 }
    66 \end{center}
    67   }
    68 \caption{Platform Hardware Specs}
    69 \label{hwinfo}
    70 \end{table}
     52%\begin{table}[htbp]
     53%{
     54%  \footnotesize
     55%  \begin{center}
     56%{
     57%\begin{tabular}{|l||@{~}l@{~}|@{~}l@{~}|@{~}l@{~}|}
     58%\hline
     59%Processor & Core2 Duo & i3-530 & Sandybridge\\ \hline
     60%Frequency &  2.13GHz & 2.93GHz & 2.80GHz \\ \hline
     61%L1 D Cache & 32KB & 32KB & 32KB \\ \hline     
     62%L2 Cache & Shared 2MB & 256KB/core & 256KB/core \\ \hline
     63%L3 Cache & --- & 4MB  & 6MB \\ \hline
     64%Max TDP & 65W & 73W &  95W \\ \hline
     65%\end{tabular}
     66%}
     67%\end{center}
     68%  }
     69%\caption{Platform Hardware Specs}
     70%\label{hwinfo}
     71%\end{table}
    7172
    7273
    7374\paragraph{Platform Hardware:}
    74 SSE SIMD extensions have been available on commodity Intel processors for
    75 over a decade since the Pentium III. They have steadily evolved with
    76 improvements in instruction latency, cache interface, register
     75SSE SIMD extensions have been available on commodity Intel processors
     76for over a decade since the Pentium III. They have steadily evolved
     77with improvements in instruction latency, cache interface, register
    7778resources, and the addition of domain specific instructions. Here we
    7879investigate SIMD extensions across three different generations of
    79 intel processors (hardware details given in Table \ref{hwinfo}). We compare
    80 the energy and performance profile of the Parabix parser on each of the platforms.
    81 We also analyze the implementation specifics of SIMD extensions under
    82 various microarchitectures as well as the newer AVX extensions supported by \SB{}.
    83 
    84 
    85 We investigate the execution profiles of each XML parser
    86 using the performance counters found in the processor.
    87 We choose several key hardware events that provide insight into the profile of each
    88 application and indicate if the processor is doing useful work
    89 ~\cite{bellosa2001, bertran2010}. 
    90 The set of events included in our study are: branch instructions, branch mispredictions,
    91 integer instructions, SIMD instructions, and cache misses. In
    92 addition, we characterize the SIMD operations and study the type and
    93 class of SIMD operations using the Intel Pin binary instrumentation
     80intel processors: Core2Duo (2.13Ghz,32KB L1, 2MB Shared L2), Core i3
     81(2.9Ghz, 32KB L1,256KB L2, 4MB Shared LLC), and Sandybridge (2.8Ghz,
     8232KB L1, 256KB L2, 6MB LLC). We compare the energy and performance
     83profile of the Parabix under the platforms.  We also analyze the
     84implementation specifics of SIMD extensions under various
     85microarchitectures and the newer AVX extensions.  We investigate the
     86execution profiles of each XML parser using the performance counters
     87found in the processor.  We choose several key hardware events that
     88provide insight into the profile of each application and indicate if
     89the processor is doing useful work ~\cite{bellosa2001, bertran2010}.
     90The set of events included in our study are: branch instructions,
     91branch mispredictions, integer instructions, SIMD instructions, and
     92cache misses. In addition, we characterize the SIMD operations and
     93study the type and class of SIMD operations using the Intel Pin
    9494framework.
    9595
     
    9898
    9999\paragraph{Energy Measurement:}
    100 A key benefit of the Parabix parser is its more efficient use of the
    101 processor pipeline which reflects in the overall energy usage.  We
    102 measure the energy consumption of the processor directly using a
     100%A key benefit of the
     101We measure the energy consumption of the processor directly using a
    103102current clamp. We apply the Fluke i410 current clamp \cite{clamp} to the 12V wires
    104103that supply power to the processor sockets. The clamp detects the
     
    111110throughout the entire execution of the program and then calculate overall
    112111total energy as  $12V*\sum^{N_{samples}}_{i=1} Sample_i$.
    113 
    114 
Note: See TracChangeset for help on using the changeset viewer.