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 Dec 26, 2008, 11:50:05 AM (10 years ago)
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 docs/ASPLOS09
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docs/ASPLOS09/asplos094cameron.tex
r251 r252 873 873 transposition. 874 874 875 The existence of highperformance algorithms for transformation of 876 character data between byte stream and parallel bit stream form 877 in both directions makes it possible to consider applying these 878 transformations multiple times during text processing applications. 879 Just as the time domain and frequency domain each have their 880 use in signal processing applications, the byte stream form and 881 parallel bit stream form can then each be used at will in 882 character stream applications. 883 884 885 886 \section{Parallel Bit Deletion} 887 888 \begin{figure*}[tbh] 875 \begin{figure*}[t] 889 876 \begin{center} 890 877 \begin{tabular}{ccccccccc} … … 904 891 \end{figure*} 905 892 893 The existence of highperformance algorithms for transformation of 894 character data between byte stream and parallel bit stream form 895 in both directions makes it possible to consider applying these 896 transformations multiple times during text processing applications. 897 Just as the time domain and frequency domain each have their 898 use in signal processing applications, the byte stream form and 899 parallel bit stream form can then each be used at will in 900 character stream applications. 901 902 903 904 \section{Parallel Bit Deletion} 905 906 906 907 Parallel bit deletion is an important operation that allows string 907 908 editing operations to be carried out while in parallel bit stream … … 1001 1002 \subsection{Parity} 1002 1003 1003 \begin{figure} 1004 \begin{figure}[h] 1004 1005 \begin{center}\small 1005 1006 \begin{verbatim} … … 1016 1017 \end{figure} 1017 1018 1018 \begin{figure} 1019 \begin{figure}[h] 1019 1020 \begin{center}\small 1020 1021 \begin{verbatim} … … 1073 1074 1074 1075 \subsection{String/Decimal/Integer Conversion} 1075 \begin{figure} 1076 \begin{figure}[h] 1076 1077 \begin{center}\small 1077 1078 \begin{verbatim} … … 1085 1086 \end{figure} 1086 1087 1087 \begin{figure} 1088 \begin{figure}[h] 1088 1089 \begin{center}\small 1089 1090 \begin{verbatim} … … 1120 1121 higher one by 10000 and adding. Overall, 20 1121 1122 operations are required for this implementation 1122 as well as the corresponding SWARimplementation1123 for sets of 32bit fields. Preloading of 6 constants1124 into registers for repeated use can reduce the number of1125 operations to 14 at the cost of significantregister1123 as well as the corresponding RefA implementation 1124 for sets of 32bit fields. Under the RefB model, preloading of 1125 6 constants into registers for repeated use can reduce the 1126 number of operations to 14 at the cost of register 1126 1127 pressure. 1127 1128 … … 1131 1132 halfoperand modifiers, with only one operand 1132 1133 of each of the addition and multiplication operations 1133 modified at each level. Overall, this implementation 1134 requires 9 operations, or 6 operations with 3 1135 preloaded constants. This represents more than a 2X 1134 modified at each level. Overall, the IDISAA implementation 1135 requires 9 operations, while the IDISAB model requires 1136 6 operations with 3 preloaded registers. 1137 In either case, this represents more than a 2X 1136 1138 reduction in instruction count as well as a 2X reduction 1137 1139 in register pressure.
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