Changeset 2698


Ignore:
Timestamp:
Nov 27, 2012, 8:09:29 AM (6 years ago)
Author:
cameron
Message:

Fixes for advance_n support in experimental mode

Files:
4 edited

Legend:

Unmodified
Added
Removed
  • proto/Compiler/CCGO.py

    r2697 r2698  
    112112        adv_index = self.advIndex[operation_no - self.operation_offset]
    113113        cq_index = adv_index + self.carry_count
    114         return [ast.Assign([ast.Subscript(self.CarryGroupAtt('cq'), ast.Index(ast.Num(cq_index)), ast.Store())], adv_out_expr)]
    115 #                          mkCall("bitblock::srli<127>", [carry_out_expr]))]
     114        return [ast.Assign([ast.Subscript(self.CarryGroupAtt('cq'), ast.Index(ast.Num(cq_index)), ast.Store())],
     115                           mkCall("bitblock::srli<64>", [adv_out_expr]))]
    116116    def GenerateCarryIfTest(self, block_no, ifTest):
    117117        carry_count = self.carryInfoSet.block_op_count[block_no]
  • proto/Compiler/pablo.py

    r2697 r2698  
    536536                carry_in_expr = mkCall('simd<1>::constant<0>', [])
    537537            callnode = assigNode.value
    538             pablo_routine_call = mkCall('pablo_blk_Advance<%i>' %  assigNode.value.args[1].n, [assigNode.value.args[0], carry_in_expr, assigNode.targets[0]])
     538            pablo_routine_call = mkCall('pablo_blk_Advance_n_<%i>' %  assigNode.value.args[1].n, [assigNode.value.args[0], carry_in_expr, assigNode.targets[0]])
    539539            self.last_stmt = pablo_routine_call
    540540            compiled = self.ccgo.GenerateAdvanceOutStore(self.operation_count, pablo_routine_call)
  • proto/parabix2/pablo_template_lsst.cpp

    r2547 r2698  
    1010#include <simd-lib/bitblock.hpp>
    1111#include <simd-lib/carryQ.hpp>
     12#include <simd-lib/pabloSupport.hpp>
    1213#include <simd-lib/bitblock_iterator.hpp>
    1314#include <simd-lib/s2p.hpp>
  • trunk/lib/pabloSupport.hpp

    r2696 r2698  
    1515}
    1616
    17 template <int n> IDISA_ALWAYS_INLINE BitBlock pablo_blk_Advance_n_(BitBlock strm, BitBlock pending_in, BitBlock & rslt) [
     17template <int n> IDISA_ALWAYS_INLINE BitBlock pablo_blk_Advance_n_(BitBlock strm, BitBlock pending_in, BitBlock & rslt) {
    1818        BitBlock half_block_shifted = esimd<BLOCK_SIZE/2>::mergel(strm, pending_in);
    1919        rslt = simd_or(simd<BLOCK_SIZE/2>::srli<(BLOCK_SIZE/2)-n>(half_block_shifted),
    2020                       simd<BLOCK_SIZE/2>::slli<n>(strm));
    21         return bitblock::srli<BLOCK_SIZE/2>(strm);
     21        return strm;
    2222}
    2323
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