Changeset 2707 for proto


Ignore:
Timestamp:
Dec 1, 2012, 6:41:55 AM (7 years ago)
Author:
cameron
Message:

Clean ups; prepare for overrides

File:
1 edited

Legend:

Unmodified
Added
Removed
  • proto/Compiler/CCGO_HMCPS.py

    r2705 r2707  
    3131  return var
    3232 
    33 def make_mergeh(fw, x, y):
    34   #return "esimd<%i>::mergeh(%s, %s)" % (fw, x, y)
    35   return make_call("esimd<%i>::mergeh" % fw, [mk_var(x), mk_var(y)])
    36 
    3733def make_assign(var, expr):
    38   #return "%s = %s;\n" % (v, expr)
    39   if isinstance(var, str):
     34   if isinstance(var, str):
    4035        var = ast.Name(var, ast.Store())
    41   return ast.Assign([var], expr)
    42 
    43 def make_zero(fw):
    44   #return "simd<%i>::constant<0>() % fw
    45   return make_call("simd<%i>::constant<0>" % fw, [])
    46 
    47 def make_index_load(var, num):
     36   return ast.Assign([var], expr)
     37
     38def make_index(var, num, mode=ast.Load()):
    4839  if isinstance(var, str):
    4940        var = ast.Name(var, ast.Load())
    50   return ast.Subscript(var, ast.Index(ast.Num(num)), ast.Load())
     41  return ast.Subscript(var, ast.Index(ast.Num(num)), mode)
    5142
    5243def make_index_store(var, num):
     
    5546  return ast.Subscript(var, ast.Index(ast.Num(num)), ast.Store())
    5647
    57 def make_att_load(var, att):
     48def make_att(var, att, mode=ast.Load()):
    5849  if isinstance(var, str):
    5950        var = ast.Name(var, ast.Load())
    60   return ast.Attribute(var, att, ast.Load())
     51  return ast.Attribute(var, att, mode)
    6152
    6253def make_att_store(var, att):
     
    7364  if isinstance(fn_name, str): fn_name = ast.Name(fn_name, ast.Load())
    7465  return ast.Expr(ast.Call(fn_name, args, [], None, None))
     66
     67def make_mergeh(fw, x, y):
     68  return make_call("esimd<%i>::mergeh" % fw, [mk_var(x), mk_var(y)])
     69
     70def make_zero(fw):
     71  return make_call("simd<%i>::constant<0>" % fw, [])
     72
    7573 
    7674#
     
    9997# carry_num carry has just been generated.
    10098#
    101 def gen_carry_pack(pack_fw, carry_num, temp_pfx):
    102   # The range of carries now to be packed depends on
    103   # the number of rightmost contiguous 1 bits
    104   carry_range_size = (carry_num + 1) &~ carry_num
    105   assign_list = []
    106   i = 2
    107   v1 = temp_pfx + repr(carry_num)
    108   v0 = temp_pfx + repr(carry_num ^ 1)
    109   fw = pack_fw
    110   while i <= carry_range_size:
    111     p = '%s%i_%i' % (temp_pfx, carry_num, carry_num - i + 1)
    112     assign_list.append(make_assign(p, make_mergeh(fw, v1, v0)))
    113     v1 = p
    114     v0 = '%s%i_%i' % (temp_pfx, carry_num - i, carry_num - 2*i+1)
    115     i *= 2
    116     fw *= 2
    117   return assign_list
    118 
    119 #
    120 # Pack in a zero carry value
    121 #
    122 def gen_carry_zero_then_pack(pack_fw, carry_num, temp_pfx):
    123   # The range of carries now to be packed depends on
    124   # the number of rightmost contiguous 1 bits
    125   carry_range_size = (carry_num + 1) &~ carry_num
    126   i = 2
    127   v1 = temp_pfx + repr(carry_num)
    128   v0 = temp_pfx + repr(carry_num ^ 1)
    129   fw = pack_fw
    130   assign_list = [make_assign(v1, make_zero(fw))]
    131   while i <= carry_range_size:
    132     p = '%s%i_%i' % (temp_pfx, carry_num, carry_num - i + 1)
    133     assign_list.append(make_assign(p, make_mergeh(fw, v1, v0)))
    134     v1 = p
    135     v0 = '%s%i_%i' % (temp_pfx, carry_num - i, carry_num - 2*i+1)
    136     i *= 2
    137     fw *= 2
    138   return assign_list
    139 
    140 
    141 
    142 #
    143 # Carry Storage/Access
    144 #
    145 # Carries are stored in one or more ubitblocks as byte values.
    146 # For each block, the carry count is rounded up to the nearest power of 2 ceiling P,
    147 # so that the carry test for that block is accessible as a single value of P bytes.
    148 # Packs of 1, 2, 4 or 8 carries are respectively represented
    149 # as one or more _8, _16, _32 or _64 values.  (Members of ubitblock union.)
    150 #
    151 #
    152 # Allocation phase determines the ubitblock_no and count for each block.
    153 
    154 #  carry-in access is a byte load  carryG[packno]._8[offset]
    155 #  carryout store is to a local pack var until we get to the final byte of a pack
    156 #
    157 #  if-test: let P be pack_size in {1,2,4,8,...}
    158 #    if P <= 8, use an integer test expression cG[packno]._%i % (P * 8)[block_offset]
    159 #     
    160 #  while test similar
    161 #    local while decl: use a copy of carryGroup
    162 #    while finalize  carry combine:   round up and |= into structure
    163 #
     99
    164100def pow2ceil(n):
    165101   c = 1
     
    200136        b_carries += aligned_size[sb]
    201137        op += cis.block_op_count[sb]
    202  #   if cis.whileblock[b] or aligned_size[b] > pack_size:
     138    # Force whiles to use full blocks; this possibly can be relaxed.
    203139    if cis.whileblock[b] or b_carries > pack_size:
    204140      aligned_size[b] = align(b_carries, pack_size)
     
    249185        self.carry_offset = 0
    250186
     187#
     188# Carry Storage/Access
     189#
     190# Carries are stored in one or more ubitblocks as byte values.
     191# For each block, the carry count is rounded up to the nearest power of 2 ceiling P,
     192# so that the carry test for that block is accessible as a single value of P bytes.
     193# Packs of 1, 2, 4 or 8 carries are respectively represented
     194# as one or more _8, _16, _32 or _64 values.  (Members of ubitblock union.)
     195#
     196#
     197# Allocation phase determines the ubitblock_no and count for each block.
     198
     199#  carry-in access is a byte load  carryG[packno]._8[offset]
     200#  carryout store is to a local pack var until we get to the final byte of a pack
     201#
     202#  if-test: let P be pack_size in {1,2,4,8,...}
     203#    if P <= 8, use an integer test expression cG[packno]._%i % (P * 8)[block_offset]
     204#     
     205#  while test similar
     206#    local while decl: use a copy of carryGroup
     207#    while finalize  carry combine:   round up and |= into structure
     208#
     209    def carry_pack_full(self, ub, mode = ast.Load()):
     210       return make_att(make_index(self.carryGroupVar, ub), '_128', mode)
     211
     212    def carry_pack_index(self, fw, ub, rp, mode = ast.Load()):
     213       return make_index(make_att(make_index(self.carryGroupVar, ub), '_%i' % fw), rp, mode)
     214
     215    def local_pack_full(self, ub, mode = ast.Load()):
     216       return make_att(make_index("sub" + self.carryGroupVar, ub), '_128', mode)
     217
     218
     219
    251220    def cg_temp(self, hi_carry, lo_carry = None):
    252221      if lo_carry == None or hi_carry == lo_carry: return "%s%i" % (self.temp_prefix, hi_carry)
     
    302271      pending = self.cg_temp(carry_num - 1, pending_carry_base)
    303272      #print shift_result, " by shift ", pending, shift
    304       a1 = make_assign(shift_result, make_call('mvmd<%i>::srli<%i>' % (self.fw, shift), [mk_var(pending)]))
     273      a1 = make_assign(shift_result, make_call('bitblock::srli<%i>' % (self.fw * shift), [mk_var(pending)]))
    305274      # Do any necessary merges
    306275      m = self.gen_merges(carry_num + shift - 1,  pending_carry_base)
     
    342311    def GenerateInitializations(self):
    343312        v = self.carryGroupVar       
    344         #const_0 = make_zero(self.fw)
    345         #inits = [make_assign(make_index_store(v, i), const_0) for i in range(0, self.ubitblock_count)]
    346313        inits = ""
    347314        for i in range(0, self.ubitblock_count):
     
    353320            rp = posn%self.field_count
    354321            inits += "%s[%i]._%i[%i] = 1;\n" % (self.carryGroupVar, ub, self.fw, rp)
    355             #v_ub = make_index_load(self.carryGroupVar, ub)
    356             #v_ub_fw = make_att_load(v_ub, '_%i' % self.fw)
    357             #inits.append(make_assign(make_index_store(v_ub_fw, rp), ast.Num(1)))
    358322        return inits
    359323    def GenerateStreamFunctionDecls(self):
     
    372336        ub = posn/self.field_count
    373337        rp = posn%self.field_count
    374         v_ub = make_index_load(self.carryGroupVar, ub)
    375         v_ub_fw = make_att_load(v_ub, '_%i' % self.fw)
    376         return make_call("convert", [make_index_load(v_ub_fw, rp)])
     338        return make_call("convert", [self.carry_pack_index(self.fw, ub, rp)])
    377339    def GenerateCarryOutStore(self, operation_no, carry_out_expr):
    378340        block_no = self.carryInfoSet.containing_block[operation_no]
     
    389351        #print (posn, skip)
    390352        if next_posn % self.field_count == 0:
    391           v_ub = make_index_load(self.carryGroupVar, ub)
    392353          shift_op = "simd<%i>::srli<%i>" % (self.fw, self.fw-1)
    393354          storable_carry_in_form = make_call(shift_op, [mk_var(self.cg_temp(self.field_count - 1, 0))])
    394           assigs.append(make_assign(make_att_store(v_ub, '_128'), storable_carry_in_form))
     355          assigs.append(make_assign(self.carry_pack_full(ub, ast.Store()), storable_carry_in_form))
    395356        return assigs
    396357    def GenerateAdvanceInAccess(self, operation_no): pass
     
    408369        count = self.aligned_size[block_no]
    409370        width = count * self.fw
    410         v_ub = make_index_load(self.carryGroupVar, ub)
    411371        if width <= 64:
    412             t = make_index_load(make_att_load(v_ub, '_%i' % width), rp/count)
     372            t = self.carry_pack_index(width, ub, rp/count)
    413373            return TestHelper_Integer_Or(testExpr, t)
    414374        else:
    415             t = make_att_load(v_ub, '_128')
     375            t = self.carry_pack_full(ub)
    416376            for i in range(1, count/self.field_count):
    417               v2 = make_att_load(make_index_load(self.carryGroupVar, ub + i), '_128')
     377              v2 = self.carry_pack_full(ub + i)
    418378              t = make_call('simd_or', [t, v2])
    419379            return TestHelper_Bitblock_Or(testExpr, t)
     
    438398        assigs = self.gen_multiple_carry_zero_then_pack(rp, end_pos - rp + 1)
    439399        if (end_pos + 1) % self.field_count == 0:
    440           v_ub = make_index_load(self.carryGroupVar, ub)
    441400          shift_op = "simd<%i>::srli<%i>" % (self.fw, self.fw-1)
    442401          storable_carry_in_form = make_call(shift_op, [mk_var(self.cg_temp(self.field_count - 1, 0))])
    443           assigs.append(make_assign(make_att_store(v_ub, '_128'), storable_carry_in_form))
    444 
     402          assigs.append(make_assign(self.carry_pack_full(ub, ast.Store()), storable_carry_in_form))
    445403        return assigs
    446404
     
    482440        rp = posn%self.field_count
    483441        count = self.aligned_size[block_no]
    484         v = self.carryGroupVar
    485         lv = "sub" + v
    486442        if count < self.field_count:
    487443          v0 = self.cg_temp(rp + count - 1, rp)
     
    491447        assigs = []
    492448        for i in range(n):
    493           v_ub_i = make_index_load(v, ub + i)
    494           assigs.append(make_assign(make_att_store(v_ub_i, '_128'), make_call('simd_or', [make_att_load(v_ub_i, '_128'), make_att_load(make_index_load(lv, i), '_128')])))
     449          assigs.append(make_assign(self.carry_pack_full(ub + i, ast.Store()), make_call('simd_or', [self.carry_pack_full(ub + i), self.local_pack_full(i)])))
    495450        return assigs
    496451    def GenerateStreamFunctionFinalization(self):
    497         if self.carryInfoSet.carry_count == 0: return []
    498         # Generate statements to shift all carries from carry-out form to carry-in form.
    499         #v = self.carryGroupVar
    500         #n = (self.aligned_size[0] + self.field_count - 1)/self.field_count
    501         #shift_op = "simd<%i>::srli<%i>" % (self.fw, self.fw-1)
    502         #return [make_assign(make_att_store(make_index_load(v, i), '_128'), make_call(shift_op, [make_att_load(make_index_load(v, i), '_128')])) for i in range(n)]
    503         #
    504         # Now arranging shifts with original stores.
    505452        return []
    506453
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