Changeset 2791 for proto/Compiler


Ignore:
Timestamp:
Dec 19, 2012, 7:19:06 AM (7 years ago)
Author:
cameron
Message:

Resolve advance_n bugs for experimental compiler mode.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • proto/Compiler/CCGO_HMCPS.py

    r2790 r2791  
    1111import CCGO
    1212
    13 # Copyright 2012, Robert D. Cameron
    14 # All rights reserved.
    1513#
    1614# Helper functions
     
    178176        self.temp_prefix = temp_prefix
    179177        self.aligned_size = determine_aligned_block_sizes(self.field_count, carryInfoSet)
    180         carry_bitblocks = (self.aligned_size[0] + self.field_count - 1) / self.field_count
    181         self.ubitblock_count = carry_bitblocks + carryInfoSet.adv_n_count
     178        self.carryblock_count = (self.aligned_size[0] + self.field_count - 1) / self.field_count
     179        self.totalblock_count = self.carryblock_count + carryInfoSet.adv_n_count
    182180        self.alloc_map = {}
    183181        self.alloc_map[0] = 0
     
    319317     
    320318    def GenerateCarryDecls(self):
    321         return "  ubitblock %s [%i];\n" % (self.carryGroupVar, self.ubitblock_count)
     319        return "  ubitblock %s [%i];\n" % (self.carryGroupVar, self.totalblock_count)
    322320    def GenerateInitializations(self):
    323321        v = self.carryGroupVar       
    324322        inits = ""
    325         for i in range(0, self.ubitblock_count):
     323        for i in range(0, self.totalblock_count):
    326324          inits += "%s[%i]._128 = simd<%i>::constant<0>();\n" % (v, i, self.fw)
    327325        for op_no in range(self.carryInfoSet.block_op_count[0]):
     
    353351        ub = posn/self.field_count
    354352        rp = posn%self.field_count
    355         # Only generate an actual store for the last carryout
     353        # Save the carry in the carry temp variable and then merge
     354        # pending carry temps as far as possible.
    356355        assigs = [make_assign(self.temp_prefix + repr(rp), carry_out_expr)]
    357356        assigs += self.gen_merges(rp, rp)
    358         next_posn = self.alloc_map[operation_no + 1] - self.carry_offset
     357        # Only generate an actual store for the last carryout in a pack.
     358        next_op = operation_no + 1
     359        while self.adv_n_map.has_key(next_op): next_op += 1
     360        next_posn = self.alloc_map[next_op] - self.carry_offset
    359361        skip = next_posn - posn - 1
    360362        if skip > 0:
     
    367369        return assigs
    368370    def GenerateAdvanceInAccess(self, operation_no):
    369         return self.carry_pack_full(self.ubitblock_count + self.adv_n_map[operation_no])
     371        return self.carry_pack_full(self.carryblock_count + self.adv_n_map[operation_no])
    370372    def GenerateAdvanceOutStore(self, operation_no, adv_out_expr):
    371         return [ast.Assign([self.carry_pack_full(self.ubitblock_count + self.adv_n_map[operation_no], mode=ast.Store())],
     373        return [ast.Assign([self.carry_pack_full(self.carryblock_count + self.adv_n_map[operation_no], mode=ast.Store())],
    372374                           make_call("bitblock::srli<64>", [adv_out_expr]))]
    373375    def GenerateTestAll(self, instance_name):
    374         if self.ubitblock_count == 0: return ast.Num(0)
     376        if self.totalblock_count == 0: return ast.Num(0)
    375377        else:
    376378            v = make_att(instance_name, self.carryGroupVar)
    377379            t = self.carry_pack_full(0, v)
    378             for i in range(1, self.ubitblock_count):
     380            for i in range(1, self.totalblock_count):
    379381              t2 = self.carry_pack_full(i, v)
    380382              t = make_call('simd_or', [t, t2])
     
    482484
    483485    def GenerateCarryDecls(self):
    484         return "  BitBlock simd_const_1\n;    BitBlock %s [%i];\n" % (self.carryGroupVar, self.ubitblock_count)
     486        return "  BitBlock simd_const_1;\n    BitBlock %s [%i];\n" % (self.carryGroupVar, self.totalblock_count)
    485487
    486488    def GenerateInitializations(self):
    487489        v = self.carryGroupVar       
    488490        inits = "simd_const_1 = mvmd<16>::srli<7>(simd<16>::constant<1>());\n"
    489         for i in range(0, self.ubitblock_count):
     491        for i in range(0, self.totalblock_count):
    490492          inits += "%s[%i] = simd<%i>::constant<0>();\n" % (v, i, self.fw)
    491493        for op_no in range(self.carryInfoSet.block_op_count[0]):
     
    530532        return decls + [make_callStmt('BitBlock_declare', [mk_var(t)]) for t in temps]
    531533   
    532 
     534# Copyright 2012, Robert D. Cameron
Note: See TracChangeset for help on using the changeset viewer.