Changeset 3504


Ignore:
Timestamp:
Sep 15, 2013, 5:18:25 PM (6 years ago)
Author:
bhull
Message:

Typos.

File:
1 edited

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  • docs/Working/re/avx2.tex

    r3500 r3504  
    22
    33
    4 Although commodity processors have provided 128-bit SIMD operations
     4Although commodity processors have provided 128-bit SIMD operations for
    55more than a decade, the extension to 256-bit integer SIMD operations
    66has just recently taken place with the availability of AVX2
     
    1313library functions using the new AVX2 intrinsics.   There were minor
    1414issues in the core transposition algorithm because the doublebyte-to-byte
    15 pack instructions are confined to independent operation within two
     15pack instructions are confined to independent operations within two
    1616128-bit lanes. 
    1717
     
    9797non destructive three-operand
    9898form instead of the destructive two-operand form of SSE2.
    99 In the two-operand form, binary instructions must always used
     99In the two-operand form, binary instructions must always use
    100100one of the source registers as a destination register.   As a
    101101result the SSE2 object code generates many data movement operations
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