Ignore:
Timestamp:
Aug 8, 2014, 11:34:47 PM (5 years ago)
Author:
linmengl
Message:

more testings done, on v64i2 add/sub/mul/eq/lt/gt/ult/ugt/vsll/vsrl/vsra

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/lib_ir/gen/impl_data.py

    r3977 r3981  
    3939    tmpAns = simd_or(simd_and(tmp, arg2), simd_and(simd_slli(curRegSize, 1, simd_and(tmp, arg2)), simd_or(tmp, arg2)))
    4040    return simd_ifh(1, simd_himask(fw), tmpAns, simd_srli(curRegSize, 1, tmpAns))''',
     41
     42"vsll_2": r'''
     43    tmp1 = b.SHL<1>(arg2)
     44    tmp = simd_or(simd_and(b.SHL<1>(arg1), tmp1), simd_and(arg1, simd_not(tmp1)))
     45    return simd_ifh(1, simd_himask(fw), tmp, simd_and(arg1, simd_not(arg2)))''',
     46
     47"vsrl_2": r'''
     48    tmp = simd_or(simd_and(arg1, simd_not(arg2)), simd_and(b.SRL<1>(arg1), arg2))
     49    return simd_ifh(1, simd_himask(fw), simd_and(arg1, simd_not(b.SHL<1>(arg2))), tmp)''',
     50
     51"vsra_2": r'''
     52    return simd_ifh(1, simd_himask(fw), arg1, simd_or(simd_and(arg1, simd_not(arg2)), simd_and(arg2, b.SRL<1>(arg1))))''',
    4153}
    4254
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