Ignore:
Timestamp:
Jul 13, 2015, 2:11:13 PM (4 years ago)
Author:
cameron
Message:

Upgrade LLVM to 3.6.1

Location:
icGREP/icgrep-devel/llvm-3.6.1.src
Files:
1 edited
1 moved

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/llvm-3.6.1.src/lib/Target/Mips/MipsSEISelLowering.cpp

    r4574 r4664  
    123123
    124124  if (Subtarget.isGP64bit()) {
     125    setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Custom);
     126    setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Custom);
    125127    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
    126128    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
     
    201203    // MIPS64r6 replaces the accumulator-based multiplies with a three register
    202204    // instruction
     205    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
     206    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
    203207    setOperationAction(ISD::MUL, MVT::i64, Legal);
    204208    setOperationAction(ISD::MULHS, MVT::i64, Legal);
     
    28802884  unsigned Lane = MI->getOperand(2).getImm();
    28812885
    2882   if (Lane == 0)
    2883     BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
    2884   else {
    2885     unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
     2886  if (Lane == 0) {
     2887    unsigned Wt = Ws;
     2888    if (!Subtarget.useOddSPReg()) {
     2889      // We must copy to an even-numbered MSA register so that the
     2890      // single-precision sub-register is also guaranteed to be even-numbered.
     2891      Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
     2892
     2893      BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
     2894    }
     2895
     2896    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
     2897  } else {
     2898    unsigned Wt = RegInfo.createVirtualRegister(
     2899        Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
     2900                                  &Mips::MSA128WEvensRegClass);
    28862901
    28872902    BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
     
    29452960  unsigned Lane = MI->getOperand(2).getImm();
    29462961  unsigned Fs = MI->getOperand(3).getReg();
    2947   unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
     2962  unsigned Wt = RegInfo.createVirtualRegister(
     2963      Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
     2964                                &Mips::MSA128WEvensRegClass);
    29482965
    29492966  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
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