Ignore:
Timestamp:
Jul 13, 2015, 2:11:13 PM (4 years ago)
Author:
cameron
Message:

Upgrade LLVM to 3.6.1

Location:
icGREP/icgrep-devel/llvm-3.6.1.src
Files:
1 edited
1 moved

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/llvm-3.6.1.src/lib/Target/R600/SIInsertWaits.cpp

    r4574 r4664  
    8383  InstType LastOpcodeType;
    8484
     85  bool LastInstWritesM0;
     86
    8587  /// \brief Get increment/decrement amount for this instruction.
    8688  Counters getHwCounts(MachineInstr &MI);
     
    106108  /// \brief Resolve all operand dependencies to counter requirements
    107109  Counters handleOperands(MachineInstr &MI);
     110
     111  /// \brief Insert S_NOP between an instruction writing M0 and S_SENDMSG.
     112  void handleSendMsg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
    108113
    109114public:
     
    270275      BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP))
    271276          .addImm(0);
     277      LastInstWritesM0 = false;
    272278    }
    273279
     
    363369
    364370  LastOpcodeType = OTHER;
     371  LastInstWritesM0 = false;
    365372  return true;
    366373}
     
    404411}
    405412
     413void SIInsertWaits::handleSendMsg(MachineBasicBlock &MBB,
     414                                  MachineBasicBlock::iterator I) {
     415  if (TRI->ST.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
     416    return;
     417
     418  // There must be "S_NOP 0" between an instruction writing M0 and S_SENDMSG.
     419  if (LastInstWritesM0 && I->getOpcode() == AMDGPU::S_SENDMSG) {
     420    BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP)).addImm(0);
     421    LastInstWritesM0 = false;
     422    return;
     423  }
     424
     425  // Set whether this instruction sets M0
     426  LastInstWritesM0 = false;
     427
     428  unsigned NumOperands = I->getNumOperands();
     429  for (unsigned i = 0; i < NumOperands; i++) {
     430    const MachineOperand &Op = I->getOperand(i);
     431
     432    if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0)
     433      LastInstWritesM0 = true;
     434  }
     435}
     436
    406437// FIXME: Insert waits listed in Table 4.2 "Required User-Inserted Wait States"
    407438// around other non-memory instructions.
     
    418449  LastIssued = ZeroCounts;
    419450  LastOpcodeType = OTHER;
     451  LastInstWritesM0 = false;
    420452
    421453  memset(&UsedRegs, 0, sizeof(UsedRegs));
     
    434466      else
    435467        Changes |= insertWait(MBB, I, handleOperands(*I));
     468
    436469      pushInstruction(MBB, I);
     470      handleSendMsg(MBB, I);
    437471    }
    438472
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