Ignore:
Timestamp:
Jul 13, 2015, 2:11:13 PM (4 years ago)
Author:
cameron
Message:

Upgrade LLVM to 3.6.1

Location:
icGREP/icgrep-devel/llvm-3.6.1.src
Files:
1 edited
1 moved

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/llvm-3.6.1.src/lib/Target/R600/SIInstrInfo.cpp

    r4574 r4664  
    122122      return false;
    123123
     124    const ConstantSDNode *Load0Offset =
     125        dyn_cast<ConstantSDNode>(Load0->getOperand(1));
     126    const ConstantSDNode *Load1Offset =
     127        dyn_cast<ConstantSDNode>(Load1->getOperand(1));
     128
     129    if (!Load0Offset || !Load1Offset)
     130      return false;
     131
    124132    // Check chain.
    125133    if (findChainOperand(Load0) != findChainOperand(Load1))
    126134      return false;
    127135
    128     Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
    129     Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
     136    Offset0 = Load0Offset->getZExtValue();
     137    Offset1 = Load1Offset->getZExtValue();
    130138    return true;
    131139  }
     
    334342
    335343  } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
     344    if (DestReg == AMDGPU::VCC) {
     345      if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
     346        BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
     347          .addReg(SrcReg, getKillRegState(KillSrc));
     348      } else {
     349        // FIXME: Hack until VReg_1 removed.
     350        assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
     351        BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
     352          .addImm(0)
     353          .addReg(SrcReg, getKillRegState(KillSrc));
     354      }
     355
     356      return;
     357    }
     358
    336359    assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
    337360    BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
     
    409432
    410433  // Try to map original to commuted opcode
    411   if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
     434  NewOpc = AMDGPU::getCommuteRev(Opcode);
     435  // Check if the commuted (REV) opcode exists on the target.
     436  if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
    412437    return NewOpc;
    413438
    414439  // Try to map commuted to original opcode
    415   if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
     440  NewOpc = AMDGPU::getCommuteOrig(Opcode);
     441  // Check if the original (non-REV) opcode exists on the target.
     442  if (NewOpc != -1 && pseudoToMCOpcode(NewOpc) != -1)
    416443    return NewOpc;
    417444
     
    11221149    }
    11231150
     1151    int RegClass = Desc.OpInfo[i].RegClass;
     1152
    11241153    switch (Desc.OpInfo[i].OperandType) {
    11251154    case MCOI::OPERAND_REGISTER:
     
    11321161      break;
    11331162    case AMDGPU::OPERAND_REG_INLINE_C:
    1134       if (MI->getOperand(i).isImm() && !isInlineConstant(MI->getOperand(i))) {
     1163      if (isLiteralConstant(MI->getOperand(i))) {
    11351164        ErrInfo = "Illegal immediate value for operand.";
    11361165        return false;
     
    11531182      continue;
    11541183
    1155     int RegClass = Desc.OpInfo[i].RegClass;
    11561184    if (RegClass != -1) {
    11571185      unsigned Reg = MI->getOperand(i).getReg();
     
    11941222    if (ConstantBusCount > 1) {
    11951223      ErrInfo = "VOP* instruction uses the constant bus more than once";
    1196       return false;
    1197     }
    1198   }
    1199 
    1200   // Verify SRC1 for VOP2 and VOPC
    1201   if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
    1202     const MachineOperand &Src1 = MI->getOperand(Src1Idx);
    1203     if (Src1.isImm()) {
    1204       ErrInfo = "VOP[2C] src1 cannot be an immediate.";
    1205       return false;
    1206     }
    1207   }
    1208 
    1209   // Verify VOP3
    1210   if (isVOP3(Opcode)) {
    1211     if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
    1212       ErrInfo = "VOP3 src0 cannot be a literal constant.";
    1213       return false;
    1214     }
    1215     if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
    1216       ErrInfo = "VOP3 src1 cannot be a literal constant.";
    1217       return false;
    1218     }
    1219     if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
    1220       ErrInfo = "VOP3 src2 cannot be a literal constant.";
    12211224      return false;
    12221225    }
     
    12931296  case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
    12941297  case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
     1298  case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
    12951299  }
    12961300}
     
    20442048      }
    20452049      break;
     2050    case AMDGPU::S_LSHL_B64:
     2051      if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
     2052        NewOpcode = AMDGPU::V_LSHLREV_B64;
     2053        swapOperands(Inst);
     2054      }
     2055      break;
     2056    case AMDGPU::S_ASHR_I64:
     2057      if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
     2058        NewOpcode = AMDGPU::V_ASHRREV_I64;
     2059        swapOperands(Inst);
     2060      }
     2061      break;
     2062    case AMDGPU::S_LSHR_B64:
     2063      if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
     2064        NewOpcode = AMDGPU::V_LSHRREV_B64;
     2065        swapOperands(Inst);
     2066      }
     2067      break;
    20462068
    20472069    case AMDGPU::S_BFE_U64:
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