Ignore:
Timestamp:
Jul 13, 2015, 2:11:13 PM (4 years ago)
Author:
cameron
Message:

Upgrade LLVM to 3.6.1

Location:
icGREP/icgrep-devel/llvm-3.6.1.src
Files:
1 edited
1 moved

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/llvm-3.6.1.src/lib/Target/R600/SIInstructions.td

    r4574 r4664  
    153153>;
    154154
    155 //defm S_FLBIT_I32_B64 : SOP1_32 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>;
    156 defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32", []>;
    157 //defm S_FLBIT_I32_I64 : SOP1_32 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>;
     155defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>;
     156defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32",
     157  [(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))]
     158>;
     159defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>;
    158160defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8",
    159161  [(set i32:$dst, (sext_inreg i32:$src0, i8))]
     
    765767
    766768
    767 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>;
    768 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>;
    769 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>;
    770 def DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>;
    771 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>;
    772 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>;
    773 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>;
    774 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>;
    775 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>;
    776 def DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>;
    777 def DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>;
    778 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>;
    779 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "ds_mskor_b32", VGPR_32>;
    780 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>;
    781 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>;
    782 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "ds_min_f32", VGPR_32>;
    783 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "ds_max_f32", VGPR_32>;
    784 
    785 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
    786 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
    787 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
    788 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
    789 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
    790 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
    791 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
    792 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
    793 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
    794 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
    795 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
    796 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
    797 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
    798 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>;
     769defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>;
     770defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>;
     771defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>;
     772defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>;
     773defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>;
     774defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>;
     775defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>;
     776defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>;
     777defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>;
     778defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>;
     779defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>;
     780defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>;
     781defm DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "ds_mskor_b32", VGPR_32>;
     782defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>;
     783defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>;
     784defm DS_MIN_F32 : DS_1A1D_NORET <0x12, "ds_min_f32", VGPR_32>;
     785defm DS_MAX_F32 : DS_1A1D_NORET <0x13, "ds_max_f32", VGPR_32>;
     786
     787defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
     788defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
     789defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
     790defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
     791defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
     792defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
     793defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
     794defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
     795defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
     796defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
     797defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
     798defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
     799defm DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
     800defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>;
    799801//def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "ds_wrxchg2_rtn_b32", VGPR_32, "ds_wrxchg2_b32">;
    800802//def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "ds_wrxchg2_rtn_b32", VGPR_32, "ds_wrxchg2st64_b32">;
    801 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
    802 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
    803 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
    804 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
     803defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
     804defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
     805defm DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
     806defm DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
    805807
    806808let SubtargetPredicate = isCI in {
    807 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">;
     809defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">;
    808810} // End isCI
    809811
    810812
    811 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>;
    812 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>;
    813 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>;
    814 def DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>;
    815 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>;
    816 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>;
    817 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>;
    818 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>;
    819 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>;
    820 def DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>;
    821 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>;
    822 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>;
    823 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "ds_mskor_b64", VReg_64>;
    824 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>;
    825 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>;
    826 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>;
    827 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>;
    828 
    829 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">;
    830 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
    831 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
    832 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
    833 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
    834 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">;
    835 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">;
    836 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">;
    837 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">;
    838 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">;
    839 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">;
    840 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
    841 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
    842 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">;
     813defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>;
     814defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>;
     815defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>;
     816defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>;
     817defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>;
     818defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>;
     819defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>;
     820defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>;
     821defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>;
     822defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>;
     823defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>;
     824defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>;
     825defm DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "ds_mskor_b64", VReg_64>;
     826defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>;
     827defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>;
     828defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>;
     829defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>;
     830
     831defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">;
     832defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
     833defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
     834defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
     835defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
     836defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">;
     837defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">;
     838defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">;
     839defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">;
     840defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">;
     841defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">;
     842defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
     843defm DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
     844defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">;
    843845//def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2_b64">;
    844846//def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2st64_b64">;
    845 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
    846 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
    847 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_f64", VReg_64, "ds_min_f64">;
    848 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_f64", VReg_64, "ds_max_f64">;
     847defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
     848defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
     849defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">;
     850defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">;
    849851
    850852//let SubtargetPredicate = isCI in {
     
    875877defm DS_READ2_B32 : DS_Load2_Helper <0x00000037, "ds_read2_b32", VReg_64>;
    876878defm DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "ds_read2st64_b32", VReg_64>;
    877 defm DS_READ2_B64 : DS_Load2_Helper <0x00000075, "ds_read2_b64", VReg_128>;
    878 defm DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "ds_read2st64_b64", VReg_128>;
     879defm DS_READ2_B64 : DS_Load2_Helper <0x00000077, "ds_read2_b64", VReg_128>;
     880defm DS_READ2ST64_B64 : DS_Load2_Helper <0x00000078, "ds_read2st64_b64", VReg_128>;
    879881
    880882//===----------------------------------------------------------------------===//
     
    882884//===----------------------------------------------------------------------===//
    883885
    884 let SubtargetPredicate = isSICI in {
    885 
    886 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "buffer_load_format_x", []>;
    887 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "buffer_load_format_xy", []>;
    888 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "buffer_load_format_xyz", []>;
    889 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "buffer_load_format_xyzw", VReg_128>;
    890 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "buffer_store_format_x", []>;
    891 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "buffer_store_format_xy", []>;
    892 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "buffer_store_format_xyz", []>;
    893 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "buffer_store_format_xyzw", []>;
     886//def BUFFER_LOAD_FORMAT_X : MUBUF_ <mubuf<0x00>, "buffer_load_format_x", []>;
     887//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <mubuf<0x01>, "buffer_load_format_xy", []>;
     888//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <mubuf<0x02>, "buffer_load_format_xyz", []>;
     889defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <mubuf<0x03>, "buffer_load_format_xyzw", VReg_128>;
     890//def BUFFER_STORE_FORMAT_X : MUBUF_ <mubuf<0x04>, "buffer_store_format_x", []>;
     891//def BUFFER_STORE_FORMAT_XY : MUBUF_ <mubuf<0x05>, "buffer_store_format_xy", []>;
     892//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <mubuf<0x06>, "buffer_store_format_xyz", []>;
     893//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <mubuf<0x07>, "buffer_store_format_xyzw", []>;
    894894defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
    895   0x00000008, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global
     895  mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global
    896896>;
    897897defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
    898   0x00000009, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global
     898  mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global
    899899>;
    900900defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
    901   0x0000000a, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global
     901  mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global
    902902>;
    903903defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
    904   0x0000000b, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global
     904  mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global
    905905>;
    906906defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
    907   0x0000000c, "buffer_load_dword", VGPR_32, i32, global_load
     907  mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, global_load
    908908>;
    909909defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
    910   0x0000000d, "buffer_load_dwordx2", VReg_64, v2i32, global_load
     910  mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, global_load
    911911>;
    912912defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
    913   0x0000000e, "buffer_load_dwordx4", VReg_128, v4i32, global_load
     913  mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, global_load
    914914>;
    915915
    916916defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
    917   0x00000018, "buffer_store_byte", VGPR_32, i32, truncstorei8_global
     917  mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global
    918918>;
    919919
    920920defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
    921   0x0000001a, "buffer_store_short", VGPR_32, i32, truncstorei16_global
     921  mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global
    922922>;
    923923
    924924defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
    925   0x0000001c, "buffer_store_dword", VGPR_32, i32, global_store
     925  mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store
    926926>;
    927927
    928928defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
    929   0x0000001d, "buffer_store_dwordx2", VReg_64, v2i32, global_store
     929  mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store
    930930>;
    931931
    932932defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
    933   0x0000001e, "buffer_store_dwordx4", VReg_128, v4i32, global_store
    934 >;
    935 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "buffer_atomic_swap", []>;
     933  mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store
     934>;
     935
    936936defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic <
    937   0x00000030, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
    938 >;
    939 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "buffer_atomic_cmpswap", []>;
     937  mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global
     938>;
     939//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", []>;
    940940defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
    941   0x00000032, "buffer_atomic_add", VGPR_32, i32, atomic_add_global
     941  mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global
    942942>;
    943943defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
    944   0x00000033, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
    945 >;
    946 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "buffer_atomic_rsub", []>;
     944  mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global
     945>;
     946//def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI
    947947defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
    948   0x00000035, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
     948  mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global
    949949>;
    950950defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
    951   0x00000036, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
     951  mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global
    952952>;
    953953defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
    954   0x00000037, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
     954  mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global
    955955>;
    956956defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
    957   0x00000038, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
     957  mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global
    958958>;
    959959defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
    960   0x00000039, "buffer_atomic_and", VGPR_32, i32, atomic_and_global
     960  mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global
    961961>;
    962962defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
    963   0x0000003a, "buffer_atomic_or", VGPR_32, i32, atomic_or_global
     963  mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global
    964964>;
    965965defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
    966   0x0000003b, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
    967 >;
    968 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "buffer_atomic_inc", []>;
    969 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "buffer_atomic_dec", []>;
    970 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "buffer_atomic_fcmpswap", []>;
    971 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "buffer_atomic_fmin", []>;
    972 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "buffer_atomic_fmax", []>;
    973 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "buffer_atomic_swap_x2", []>;
    974 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "buffer_atomic_cmpswap_x2", []>;
    975 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "buffer_atomic_add_x2", []>;
    976 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "buffer_atomic_sub_x2", []>;
    977 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "buffer_atomic_rsub_x2", []>;
    978 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "buffer_atomic_smin_x2", []>;
    979 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "buffer_atomic_umin_x2", []>;
    980 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "buffer_atomic_smax_x2", []>;
    981 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "buffer_atomic_umax_x2", []>;
    982 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "buffer_atomic_and_x2", []>;
    983 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "buffer_atomic_or_x2", []>;
    984 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "buffer_atomic_xor_x2", []>;
    985 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "buffer_atomic_inc_x2", []>;
    986 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "buffer_atomic_dec_x2", []>;
    987 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "buffer_atomic_fcmpswap_x2", []>;
    988 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "buffer_atomic_fmin_x2", []>;
    989 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "buffer_atomic_fmax_x2", []>;
    990 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "buffer_wbinvl1_sc", []>;
    991 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "buffer_wbinvl1", []>;
    992 
    993 } // End SubtargetPredicate = isSICI
     966  mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global
     967>;
     968//def BUFFER_ATOMIC_INC : MUBUF_ <mubuf<0x3c, 0x4b>, "buffer_atomic_inc", []>;
     969//def BUFFER_ATOMIC_DEC : MUBUF_ <mubuf<0x3d, 0x4c>, "buffer_atomic_dec", []>;
     970//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI
     971//def BUFFER_ATOMIC_FMIN : MUBUF_ <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI
     972//def BUFFER_ATOMIC_FMAX : MUBUF_ <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI
     973//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", []>;
     974//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", []>;
     975//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <mubuf<0x52, 0x62>, "buffer_atomic_add_x2", []>;
     976//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", []>;
     977//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI
     978//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", []>;
     979//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", []>;
     980//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", []>;
     981//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", []>;
     982//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <mubuf<0x59, 0x68>, "buffer_atomic_and_x2", []>;
     983//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", []>;
     984//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", []>;
     985//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", []>;
     986//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", []>;
     987//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI
     988//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI
     989//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI
     990//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <mubuf<0x70>, "buffer_wbinvl1_sc", []>; // isn't on CI & VI
     991//def BUFFER_WBINVL1_VOL : MUBUF_WBINVL1 <mubuf<0x70, 0x3f>, "buffer_wbinvl1_vol", []>; // isn't on SI
     992//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <mubuf<0x71, 0x3e>, "buffer_wbinvl1", []>;
    994993
    995994//===----------------------------------------------------------------------===//
     
    10381037//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>;
    10391038//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>;
    1040 defm IMAGE_SAMPLE           : MIMG_Sampler <0x00000020, "image_sample">;
    1041 defm IMAGE_SAMPLE_CL        : MIMG_Sampler <0x00000021, "image_sample_cl">;
     1039defm IMAGE_SAMPLE           : MIMG_Sampler_WQM <0x00000020, "image_sample">;
     1040defm IMAGE_SAMPLE_CL        : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">;
    10421041defm IMAGE_SAMPLE_D         : MIMG_Sampler <0x00000022, "image_sample_d">;
    10431042defm IMAGE_SAMPLE_D_CL      : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
    10441043defm IMAGE_SAMPLE_L         : MIMG_Sampler <0x00000024, "image_sample_l">;
    1045 defm IMAGE_SAMPLE_B         : MIMG_Sampler <0x00000025, "image_sample_b">;
    1046 defm IMAGE_SAMPLE_B_CL      : MIMG_Sampler <0x00000026, "image_sample_b_cl">;
     1044defm IMAGE_SAMPLE_B         : MIMG_Sampler_WQM <0x00000025, "image_sample_b">;
     1045defm IMAGE_SAMPLE_B_CL      : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">;
    10471046defm IMAGE_SAMPLE_LZ        : MIMG_Sampler <0x00000027, "image_sample_lz">;
    1048 defm IMAGE_SAMPLE_C         : MIMG_Sampler <0x00000028, "image_sample_c">;
    1049 defm IMAGE_SAMPLE_C_CL      : MIMG_Sampler <0x00000029, "image_sample_c_cl">;
     1047defm IMAGE_SAMPLE_C         : MIMG_Sampler_WQM <0x00000028, "image_sample_c">;
     1048defm IMAGE_SAMPLE_C_CL      : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">;
    10501049defm IMAGE_SAMPLE_C_D       : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
    10511050defm IMAGE_SAMPLE_C_D_CL    : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
    10521051defm IMAGE_SAMPLE_C_L       : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
    1053 defm IMAGE_SAMPLE_C_B       : MIMG_Sampler <0x0000002d, "image_sample_c_b">;
    1054 defm IMAGE_SAMPLE_C_B_CL    : MIMG_Sampler <0x0000002e, "image_sample_c_b_cl">;
     1052defm IMAGE_SAMPLE_C_B       : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">;
     1053defm IMAGE_SAMPLE_C_B_CL    : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">;
    10551054defm IMAGE_SAMPLE_C_LZ      : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
    1056 defm IMAGE_SAMPLE_O         : MIMG_Sampler <0x00000030, "image_sample_o">;
    1057 defm IMAGE_SAMPLE_CL_O      : MIMG_Sampler <0x00000031, "image_sample_cl_o">;
     1055defm IMAGE_SAMPLE_O         : MIMG_Sampler_WQM <0x00000030, "image_sample_o">;
     1056defm IMAGE_SAMPLE_CL_O      : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">;
    10581057defm IMAGE_SAMPLE_D_O       : MIMG_Sampler <0x00000032, "image_sample_d_o">;
    10591058defm IMAGE_SAMPLE_D_CL_O    : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
    10601059defm IMAGE_SAMPLE_L_O       : MIMG_Sampler <0x00000034, "image_sample_l_o">;
    1061 defm IMAGE_SAMPLE_B_O       : MIMG_Sampler <0x00000035, "image_sample_b_o">;
    1062 defm IMAGE_SAMPLE_B_CL_O    : MIMG_Sampler <0x00000036, "image_sample_b_cl_o">;
     1060defm IMAGE_SAMPLE_B_O       : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">;
     1061defm IMAGE_SAMPLE_B_CL_O    : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">;
    10631062defm IMAGE_SAMPLE_LZ_O      : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
    1064 defm IMAGE_SAMPLE_C_O       : MIMG_Sampler <0x00000038, "image_sample_c_o">;
    1065 defm IMAGE_SAMPLE_C_CL_O    : MIMG_Sampler <0x00000039, "image_sample_c_cl_o">;
     1063defm IMAGE_SAMPLE_C_O       : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">;
     1064defm IMAGE_SAMPLE_C_CL_O    : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">;
    10661065defm IMAGE_SAMPLE_C_D_O     : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
    10671066defm IMAGE_SAMPLE_C_D_CL_O  : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
    10681067defm IMAGE_SAMPLE_C_L_O     : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
    1069 defm IMAGE_SAMPLE_C_B_O     : MIMG_Sampler <0x0000003d, "image_sample_c_b_o">;
    1070 defm IMAGE_SAMPLE_C_B_CL_O  : MIMG_Sampler <0x0000003e, "image_sample_c_b_cl_o">;
     1068defm IMAGE_SAMPLE_C_B_O     : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">;
     1069defm IMAGE_SAMPLE_C_B_CL_O  : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">;
    10711070defm IMAGE_SAMPLE_C_LZ_O    : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
    1072 defm IMAGE_GATHER4          : MIMG_Gather <0x00000040, "image_gather4">;
    1073 defm IMAGE_GATHER4_CL       : MIMG_Gather <0x00000041, "image_gather4_cl">;
     1071defm IMAGE_GATHER4          : MIMG_Gather_WQM <0x00000040, "image_gather4">;
     1072defm IMAGE_GATHER4_CL       : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">;
    10741073defm IMAGE_GATHER4_L        : MIMG_Gather <0x00000044, "image_gather4_l">;
    1075 defm IMAGE_GATHER4_B        : MIMG_Gather <0x00000045, "image_gather4_b">;
    1076 defm IMAGE_GATHER4_B_CL     : MIMG_Gather <0x00000046, "image_gather4_b_cl">;
     1074defm IMAGE_GATHER4_B        : MIMG_Gather_WQM <0x00000045, "image_gather4_b">;
     1075defm IMAGE_GATHER4_B_CL     : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">;
    10771076defm IMAGE_GATHER4_LZ       : MIMG_Gather <0x00000047, "image_gather4_lz">;
    1078 defm IMAGE_GATHER4_C        : MIMG_Gather <0x00000048, "image_gather4_c">;
    1079 defm IMAGE_GATHER4_C_CL     : MIMG_Gather <0x00000049, "image_gather4_c_cl">;
     1077defm IMAGE_GATHER4_C        : MIMG_Gather_WQM <0x00000048, "image_gather4_c">;
     1078defm IMAGE_GATHER4_C_CL     : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">;
    10801079defm IMAGE_GATHER4_C_L      : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
    1081 defm IMAGE_GATHER4_C_B      : MIMG_Gather <0x0000004d, "image_gather4_c_b">;
    1082 defm IMAGE_GATHER4_C_B_CL   : MIMG_Gather <0x0000004e, "image_gather4_c_b_cl">;
     1080defm IMAGE_GATHER4_C_B      : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">;
     1081defm IMAGE_GATHER4_C_B_CL   : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">;
    10831082defm IMAGE_GATHER4_C_LZ     : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
    1084 defm IMAGE_GATHER4_O        : MIMG_Gather <0x00000050, "image_gather4_o">;
    1085 defm IMAGE_GATHER4_CL_O     : MIMG_Gather <0x00000051, "image_gather4_cl_o">;
     1083defm IMAGE_GATHER4_O        : MIMG_Gather_WQM <0x00000050, "image_gather4_o">;
     1084defm IMAGE_GATHER4_CL_O     : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">;
    10861085defm IMAGE_GATHER4_L_O      : MIMG_Gather <0x00000054, "image_gather4_l_o">;
    1087 defm IMAGE_GATHER4_B_O      : MIMG_Gather <0x00000055, "image_gather4_b_o">;
     1086defm IMAGE_GATHER4_B_O      : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">;
    10881087defm IMAGE_GATHER4_B_CL_O   : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
    10891088defm IMAGE_GATHER4_LZ_O     : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
    1090 defm IMAGE_GATHER4_C_O      : MIMG_Gather <0x00000058, "image_gather4_c_o">;
    1091 defm IMAGE_GATHER4_C_CL_O   : MIMG_Gather <0x00000059, "image_gather4_c_cl_o">;
     1089defm IMAGE_GATHER4_C_O      : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">;
     1090defm IMAGE_GATHER4_C_CL_O   : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">;
    10921091defm IMAGE_GATHER4_C_L_O    : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
    1093 defm IMAGE_GATHER4_C_B_O    : MIMG_Gather <0x0000005d, "image_gather4_c_b_o">;
    1094 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "image_gather4_c_b_cl_o">;
     1092defm IMAGE_GATHER4_C_B_O    : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">;
     1093defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">;
    10951094defm IMAGE_GATHER4_C_LZ_O   : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
    1096 defm IMAGE_GET_LOD          : MIMG_Sampler <0x00000060, "image_get_lod">;
     1095defm IMAGE_GET_LOD          : MIMG_Sampler_WQM <0x00000060, "image_get_lod">;
    10971096defm IMAGE_SAMPLE_CD        : MIMG_Sampler <0x00000068, "image_sample_cd">;
    10981097defm IMAGE_SAMPLE_CD_CL     : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
     
    14461445defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32,
    14471446  fmaxnum>;
    1448 defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32,
    1449   AMDGPUsmin
    1450 >;
    1451 defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32,
    1452   AMDGPUsmax
    1453 >;
    1454 defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32,
    1455   AMDGPUumin
    1456 >;
    1457 defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32,
    1458   AMDGPUumax
    1459 >;
    1460 
    1461 // No non-Rev Op on VI
     1447defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>;
     1448defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>;
     1449defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>;
     1450defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>;
     1451
    14621452defm V_LSHRREV_B32 : VOP2Inst <
    14631453  vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag,
    1464     "v_lshr_b32", "v_lshrrev_b32"
    1465 >;
    1466 
    1467 // No non-Rev OP on VI
     1454    "v_lshr_b32"
     1455>;
     1456
    14681457defm V_ASHRREV_I32 : VOP2Inst <
    14691458  vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag,
    1470     "v_ashr_i32", "v_ashrrev_i32"
    1471 >;
    1472 
    1473 // No non-Rev OP on VI
     1459    "v_ashr_i32"
     1460>;
     1461
    14741462defm V_LSHLREV_B32 : VOP2Inst <
    14751463  vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
    1476     "v_lshl_b32", "v_lshlrev_b32"
    1477 >;
    1478 
    1479 defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32",
    1480   VOP_I32_I32_I32, and>;
    1481 defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32",
    1482   VOP_I32_I32_I32, or
    1483 >;
    1484 defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32",
    1485   VOP_I32_I32_I32, xor
    1486 >;
     1464    "v_lshl_b32"
     1465>;
     1466
     1467defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
     1468defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
     1469defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
    14871470
    14881471defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_F32_F32_F32>;
    14891472} // End isCommutable = 1
    14901473
    1491 defm V_MADMK_F32 : VOP2Inst <vop2<0x20, 0x17>, "v_madmk_f32", VOP_F32_F32_F32>;
     1474defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32">;
    14921475
    14931476let isCommutable = 1 in {
    1494 defm V_MADAK_F32 : VOP2Inst <vop2<0x21, 0x18>, "v_madak_f32", VOP_F32_F32_F32>;
     1477defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32">;
    14951478} // End isCommutable = 1
    14961479
     
    15041487  VOP_I32_I32_I32, add
    15051488>;
    1506 defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32",
    1507   VOP_I32_I32_I32, sub
    1508 >;
     1489defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP_I32_I32_I32>;
    15091490
    15101491defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32",
     
    15141495let Uses = [VCC] in { // Carry-in comes from VCC
    15151496defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
    1516   VOP_I32_I32_I32_VCC, adde
     1497  VOP_I32_I32_I32_VCC
    15171498>;
    15181499defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
    1519   VOP_I32_I32_I32_VCC, sube
     1500  VOP_I32_I32_I32_VCC
    15201501>;
    15211502defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
     
    15301511  "v_readlane_b32",
    15311512  (outs SReg_32:$vdst),
    1532   (ins VGPR_32:$src0, SSrc_32:$vsrc1),
    1533   "v_readlane_b32 $vdst, $src0, $vsrc1"
     1513  (ins VGPR_32:$src0, SCSrc_32:$src1),
     1514  "v_readlane_b32 $vdst, $src0, $src1"
    15341515>;
    15351516
     
    15381519  "v_writelane_b32",
    15391520  (outs VGPR_32:$vdst),
    1540   (ins SReg_32:$src0, SSrc_32:$vsrc1),
    1541   "v_writelane_b32 $vdst, $src0, $vsrc1"
     1521  (ins SReg_32:$src0, SCSrc_32:$src1),
     1522  "v_writelane_b32 $vdst, $src0, $src1"
    15421523>;
    15431524
     
    15451526let SubtargetPredicate = isSICI in {
    15461527
     1528defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
     1529  VOP_F32_F32_F32, AMDGPUfmin_legacy
     1530>;
     1531defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32",
     1532  VOP_F32_F32_F32, AMDGPUfmax_legacy
     1533>;
     1534
    15471535let isCommutable = 1 in {
    1548 defm V_MAC_LEGACY_F32 : VOP2Inst <vop2<0x6>, "v_mac_legacy_f32",
    1549   VOP_F32_F32_F32
    1550 >;
    1551 } // End isCommutable = 1
    1552 
    1553 defm V_MIN_LEGACY_F32 : VOP2Inst <vop2<0xd>, "v_min_legacy_f32",
    1554   VOP_F32_F32_F32, AMDGPUfmin_legacy
    1555 >;
    1556 defm V_MAX_LEGACY_F32 : VOP2Inst <vop2<0xe>, "v_max_legacy_f32",
    1557   VOP_F32_F32_F32, AMDGPUfmax_legacy
    1558 >;
    1559 
    1560 let isCommutable = 1 in {
    1561 defm V_LSHR_B32 : VOP2Inst <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32, srl>;
    1562 defm V_ASHR_I32 : VOP2Inst <vop2<0x17>, "v_ashr_i32",
    1563   VOP_I32_I32_I32, sra
    1564 >;
    1565 
    1566 let hasPostISelHook = 1 in {
    1567 defm V_LSHL_B32 : VOP2Inst <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32, shl>;
    1568 }
    1569 
     1536defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>;
     1537defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>;
     1538defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>;
    15701539} // End isCommutable = 1
    15711540} // End let SubtargetPredicate = SICI
    15721541
     1542let isCommutable = 1 in {
     1543defm V_MAC_LEGACY_F32 : VOP2_VI3_Inst <vop23<0x6, 0x28e>, "v_mac_legacy_f32",
     1544  VOP_F32_F32_F32
     1545>;
     1546} // End isCommutable = 1
     1547
    15731548defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", VOP_I32_I32_I32,
    15741549  AMDGPUbfm
     
    15871562>;
    15881563
    1589 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "v_cvt_pkaccum_u8_f32", []>;
    1590 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "v_cvt_pknorm_i16_f32", []>;
    1591 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "v_cvt_pknorm_u16_f32", []>;
     1564
     1565defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32",
     1566  VOP_I32_F32_I32>; // TODO: set "Uses = dst"
     1567
     1568defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32",
     1569  VOP_I32_F32_F32
     1570>;
     1571defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32",
     1572  VOP_I32_F32_F32
     1573>;
    15921574defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
    1593  VOP_I32_F32_F32, int_SI_packf16
    1594 >;
    1595 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "v_cvt_pk_u16_u32", []>;
    1596 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "v_cvt_pk_i16_i32", []>;
     1575  VOP_I32_F32_F32, int_SI_packf16
     1576>;
     1577defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32",
     1578  VOP_I32_I32_I32
     1579>;
     1580defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32",
     1581  VOP_I32_I32_I32
     1582>;
    15971583
    15981584//===----------------------------------------------------------------------===//
     
    16601646>;
    16611647
    1662 defm V_MIN3_F32 : VOP3Inst <vop3<0x151>, "v_min3_f32",
     1648defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32",
    16631649  VOP_F32_F32_F32_F32, AMDGPUfmin3>;
    16641650
    1665 defm V_MIN3_I32 : VOP3Inst <vop3<0x152>, "v_min3_i32",
     1651defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32",
    16661652  VOP_I32_I32_I32_I32, AMDGPUsmin3
    16671653>;
    1668 defm V_MIN3_U32 : VOP3Inst <vop3<0x153>, "v_min3_u32",
     1654defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32",
    16691655  VOP_I32_I32_I32_I32, AMDGPUumin3
    16701656>;
    1671 defm V_MAX3_F32 : VOP3Inst <vop3<0x154>, "v_max3_f32",
     1657defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32",
    16721658  VOP_F32_F32_F32_F32, AMDGPUfmax3
    16731659>;
    1674 defm V_MAX3_I32 : VOP3Inst <vop3<0x155>, "v_max3_i32",
     1660defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32",
    16751661  VOP_I32_I32_I32_I32, AMDGPUsmax3
    16761662>;
    1677 defm V_MAX3_U32 : VOP3Inst <vop3<0x156>, "v_max3_u32",
     1663defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
    16781664  VOP_I32_I32_I32_I32, AMDGPUumax3
    16791665>;
    1680 //def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>;
    1681 //def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>;
    1682 //def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>;
     1666defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
     1667  VOP_F32_F32_F32_F32
     1668>;
     1669defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
     1670  VOP_I32_I32_I32_I32
     1671>;
     1672defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
     1673  VOP_I32_I32_I32_I32
     1674>;
     1675
    16831676//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>;
    16841677//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>;
     
    17431736} // isCommutable = 1, SchedRW = [WriteQuarterRate32]
    17441737
     1738let SchedRW = [WriteFloatFMA, WriteSALU] in {
    17451739defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d, 0x1e0>, "v_div_scale_f32", []>;
    1746 
    1747 let SchedRW = [WriteDouble] in {
     1740}
     1741
     1742let SchedRW = [WriteDouble, WriteSALU] in {
    17481743// Double precision division pre-scale.
    17491744defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>;
    17501745} // let SchedRW = [WriteDouble]
    17511746
    1752 let isCommutable = 1 in {
    1753 defm V_DIV_FMAS_F32 : VOP3Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
     1747let isCommutable = 1, Uses = [VCC] in {
     1748
     1749// v_div_fmas_f32:
     1750//   result = src0 * src1 + src2
     1751//   if (vcc)
     1752//     result *= 2^32
     1753//
     1754defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
    17541755  VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
    17551756>;
     1757
    17561758let SchedRW = [WriteDouble] in {
    1757 defm V_DIV_FMAS_F64 : VOP3Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
     1759// v_div_fmas_f64:
     1760//   result = src0 * src1 + src2
     1761//   if (vcc)
     1762//     result *= 2^64
     1763//
     1764defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
    17581765  VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
    17591766>;
     1767
    17601768} // End SchedRW = [WriteDouble]
    17611769} // End isCommutable = 1
     
    17751783let SubtargetPredicate = isSICI in {
    17761784
    1777 defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64",
    1778   VOP_I64_I64_I32, shl
    1779 >;
    1780 
    1781 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64",
    1782   VOP_I64_I64_I32, srl
    1783 >;
    1784 
    1785 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64",
    1786   VOP_I64_I64_I32, sra
    1787 >;
     1785defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>;
     1786defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>;
     1787defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>;
    17881788
    17891789defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
     
    17911791
    17921792} // End SubtargetPredicate = isSICI
     1793
     1794let SubtargetPredicate = isVI in {
     1795
     1796defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
     1797  VOP_I64_I32_I64
     1798>;
     1799defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64",
     1800  VOP_I64_I32_I64
     1801>;
     1802defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
     1803  VOP_I64_I32_I64
     1804>;
     1805
     1806} // End SubtargetPredicate = isVI
    17931807
    17941808//===----------------------------------------------------------------------===//
     
    18101824// and should be lowered to ISA instructions prior to codegen.
    18111825
    1812 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
    1813     Uses = [EXEC], Defs = [EXEC] in {
     1826let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
     1827let Uses = [EXEC], Defs = [EXEC] in {
    18141828
    18151829let isBranch = 1, isTerminator = 1 in {
     
    18681882>;
    18691883
     1884} // End Uses = [EXEC], Defs = [EXEC]
     1885
     1886let Uses = [EXEC], Defs = [EXEC,VCC] in {
    18701887def SI_KILL : InstSI <
    18711888  (outs),
     
    18741891  [(int_AMDGPU_kill f32:$src)]
    18751892>;
     1893} // End Uses = [EXEC], Defs = [EXEC,VCC]
    18761894
    18771895} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
    1878   // Uses = [EXEC], Defs = [EXEC]
    18791896
    18801897let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
     
    20212038>;
    20222039
    2023 let Predicates = [isSICI] in {
    2024 
    20252040/* int_SI_vs_load_input */
    20262041def : Pat<
     
    20282043  (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
    20292044>;
    2030 
    2031 } // End Predicates = [isSICI]
    20322045
    20332046/* int_SI_export */
     
    21572170
    21582171let Predicates = [UnsafeFPMath] in {
    2159 def : RcpPat<V_RCP_F64_e32, f64>;
    2160 defm : RsqPat<V_RSQ_F64_e32, f64>;
    2161 defm : RsqPat<V_RSQ_F32_e32, f32>;
     2172
     2173//def : RcpPat<V_RCP_F64_e32, f64>;
     2174//defm : RsqPat<V_RSQ_F64_e32, f64>;
     2175//defm : RsqPat<V_RSQ_F32_e32, f32>;
     2176
     2177def : RsqPat<V_RSQ_F32_e32, f32>;
     2178def : RsqPat<V_RSQ_F64_e32, f64>;
    21622179}
    21632180
     
    26762693>;
    26772694
    2678 def : Pat<
    2679   (fdiv f64:$src0, f64:$src1),
    2680   (V_MUL_F64 0 /* src0_modifiers */, $src0,
    2681              0 /* src1_modifiers */, (V_RCP_F64_e32 $src1),
    2682              0 /* clamp */, 0 /* omod */)
    2683 >;
    2684 
    26852695def : Pat <
    26862696  (int_AMDGPU_cube v4f32:$src),
     
    27172727def : Ext32Pat <anyext>;
    27182728
    2719 let Predicates = [isSICI] in {
    2720 
    27212729// Offset in an 32Bit VGPR
    27222730def : Pat <
     
    27242732  (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
    27252733>;
    2726 
    2727 } // End Predicates = [isSICI]
    27282734
    27292735// The multiplication scales from [0,1] to the unsigned integer range
     
    29082914>;
    29092915
    2910 let Predicates = [isSICI] in {
    29112916def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
    29122917def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
     
    29162921def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
    29172922def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
    2918 } // End Predicates = [isSICI]
    29192923
    29202924// BUFFER_LOAD_DWORD*, addr64=0
     
    29552959}
    29562960
    2957 let Predicates = [isSICI] in {
    29582961defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
    29592962                         BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
     
    29622965defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
    29632966                         BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
    2964 } // End Predicates = [isSICI]
    29652967
    29662968class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
     
    29702972>;
    29712973
    2972 let Predicates = [isSICI] in {
    29732974def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
    29742975def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
     
    29762977def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
    29772978def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
    2978 } // End Predicates = [isSICI]
    29792979
    29802980/*
     
    32473247
    32483248def : Pat <
     3249  (i1 (trunc i64:$a)),
     3250  (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1),
     3251                    (EXTRACT_SUBREG $a, sub0)), 1)
     3252>;
     3253
     3254def : Pat <
    32493255  (i32 (bswap i32:$a)),
    32503256  (V_BFI_B32 (S_MOV_B32 0x00ff00ff),
     
    32583264>;
    32593265
     3266//===----------------------------------------------------------------------===//
     3267// Fract Patterns
     3268//===----------------------------------------------------------------------===//
     3269
     3270let Predicates = [isCI] in {
     3271
     3272// Convert (x - floor(x)) to fract(x)
     3273def : Pat <
     3274  (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
     3275             (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
     3276  (V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
     3277>;
     3278
     3279// Convert (x + (-floor(x))) to fract(x)
     3280def : Pat <
     3281  (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
     3282             (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
     3283  (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
     3284>;
     3285
     3286} // End Predicates = [isCI]
     3287
    32603288//============================================================================//
    32613289// Miscellaneous Optimization Patterns
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