Ignore:
Timestamp:
Jul 13, 2015, 2:11:13 PM (4 years ago)
Author:
cameron
Message:

Upgrade LLVM to 3.6.1

Location:
icGREP/icgrep-devel/llvm-3.6.1.src
Files:
1 edited
1 moved

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/llvm-3.6.1.src/lib/Target/R600/SILowerControlFlow.cpp

    r4574 r4664  
    8989  void Branch(MachineInstr &MI);
    9090
    91   void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
     91  void LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset = 0);
     92  void computeIndirectRegAndOffset(unsigned VecReg, unsigned &Reg, int &Offset);
    9293  void IndirectSrc(MachineInstr &MI);
    9394  void IndirectDst(MachineInstr &MI);
     
    324325}
    325326
    326 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
     327void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset) {
    327328
    328329  MachineBasicBlock &MBB = *MI.getParent();
     
    334335
    335336  if (AMDGPU::SReg_32RegClass.contains(Idx)) {
    336     BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
    337             .addReg(Idx);
     337    if (Offset) {
     338      BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
     339              .addReg(Idx)
     340              .addImm(Offset);
     341    } else {
     342      BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
     343              .addReg(Idx);
     344    }
    338345    MBB.insert(I, MovRel);
    339346  } else {
     
    364371            .addReg(AMDGPU::VCC);
    365372
     373    if (Offset) {
     374      BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
     375              .addReg(AMDGPU::M0)
     376              .addImm(Offset);
     377    }
    366378    // Do the actual move
    367379    MBB.insert(I, MovRel);
     
    385397}
    386398
     399/// \param @VecReg The register which holds element zero of the vector
     400///                 being addressed into.
     401/// \param[out] @Reg The base register to use in the indirect addressing instruction.
     402/// \param[in,out] @Offset As an input, this is the constant offset part of the
     403//                         indirect Index. e.g. v0 = v[VecReg + Offset]
     404//                         As an output, this is a constant value that needs
     405//                         to be added to the value stored in M0.
     406void SILowerControlFlowPass::computeIndirectRegAndOffset(unsigned VecReg,
     407                                                         unsigned &Reg,
     408                                                         int &Offset) {
     409  unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0);
     410  if (!SubReg)
     411    SubReg = VecReg;
     412
     413  const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg);
     414  int RegIdx = TRI->getHWRegIndex(SubReg) + Offset;
     415
     416  if (RegIdx < 0) {
     417    Offset = RegIdx;
     418    RegIdx = 0;
     419  } else {
     420    Offset = 0;
     421  }
     422
     423  Reg = RC->getRegister(RegIdx);
     424}
     425
    387426void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
    388427
     
    392431  unsigned Dst = MI.getOperand(0).getReg();
    393432  unsigned Vec = MI.getOperand(2).getReg();
    394   unsigned Off = MI.getOperand(4).getImm();
    395   unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
    396   if (!SubReg)
    397     SubReg = Vec;
     433  int Off = MI.getOperand(4).getImm();
     434  unsigned Reg;
     435
     436  computeIndirectRegAndOffset(Vec, Reg, Off);
    398437
    399438  MachineInstr *MovRel =
    400439    BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
    401             .addReg(SubReg + Off)
     440            .addReg(Reg)
    402441            .addReg(AMDGPU::M0, RegState::Implicit)
    403442            .addReg(Vec, RegState::Implicit);
    404443
    405   LoadM0(MI, MovRel);
     444  LoadM0(MI, MovRel, Off);
    406445}
    407446
     
    412451
    413452  unsigned Dst = MI.getOperand(0).getReg();
    414   unsigned Off = MI.getOperand(4).getImm();
     453  int Off = MI.getOperand(4).getImm();
    415454  unsigned Val = MI.getOperand(5).getReg();
    416   unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
    417   if (!SubReg)
    418     SubReg = Dst;
     455  unsigned Reg;
     456
     457  computeIndirectRegAndOffset(Dst, Reg, Off);
    419458
    420459  MachineInstr *MovRel =
    421460    BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
    422             .addReg(SubReg + Off, RegState::Define)
     461            .addReg(Reg, RegState::Define)
    423462            .addReg(Val)
    424463            .addReg(AMDGPU::M0, RegState::Implicit)
    425464            .addReg(Dst, RegState::Implicit);
    426465
    427   LoadM0(MI, MovRel);
     466  LoadM0(MI, MovRel, Off);
    428467}
    429468
     
    448487
    449488      MachineInstr &MI = *I;
    450       if (TII->isDS(MI.getOpcode()))
     489      if (TII->isWQM(MI.getOpcode()) || TII->isDS(MI.getOpcode()))
    451490        NeedWQM = true;
    452491
     
    514553          IndirectDst(MI);
    515554          break;
    516 
    517         case AMDGPU::V_INTERP_P1_F32:
    518         case AMDGPU::V_INTERP_P2_F32:
    519         case AMDGPU::V_INTERP_MOV_F32:
    520           NeedWQM = true;
    521           break;
    522555      }
    523556    }
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