Ignore:
Timestamp:
Jul 13, 2015, 2:11:13 PM (4 years ago)
Author:
cameron
Message:

Upgrade LLVM to 3.6.1

Location:
icGREP/icgrep-devel/llvm-3.6.1.src
Files:
1 edited
1 moved

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/llvm-3.6.1.src/test/CodeGen/R600/store.ll

    r4574 r4664  
    1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI-CHECK -check-prefix=FUNC %s
    2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG-CHECK -check-prefix=FUNC %s
    3 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM-CHECK -check-prefix=FUNC %s
     1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
     2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
     3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
     4; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
    45
    56;===------------------------------------------------------------------------===;
     
    78;===------------------------------------------------------------------------===;
    89; FUNC-LABEL: {{^}}store_i1:
    9 ; EG-CHECK: MEM_RAT MSKOR
    10 ; SI-CHECK: buffer_store_byte
     10; EG: MEM_RAT MSKOR
     11; SI: buffer_store_byte
    1112define void @store_i1(i1 addrspace(1)* %out) {
    1213entry:
     
    1617
    1718; i8 store
    18 ; EG-CHECK-LABEL: {{^}}store_i8:
    19 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
     19; EG-LABEL: {{^}}store_i8:
     20; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
    2021
    2122; IG 0: Get the byte index and truncate the value
    22 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
    23 ; EG-CHECK: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
    24 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
    25 ; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43)
     23; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
     24; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
     25; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
     26; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)
    2627
    2728
     
    2930
    3031; IG 2: Shift the value and the mask
    31 ; EG-CHECK: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
    32 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
    33 ; EG-CHECK-NEXT: 255
     32; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
     33; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
     34; EG-NEXT: 255
    3435; IG 3: Initialize the Y and Z channels to zero
    3536;       XXX: An optimal scheduler should merge this into one of the prevous IGs.
    36 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
    37 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
    38 
    39 ; SI-CHECK-LABEL: {{^}}store_i8:
    40 ; SI-CHECK: buffer_store_byte
     37; EG: MOV T[[RW_GPR]].Y, 0.0
     38; EG: MOV * T[[RW_GPR]].Z, 0.0
     39
     40; SI-LABEL: {{^}}store_i8:
     41; SI: buffer_store_byte
    4142
    4243define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
     
    4748
    4849; i16 store
    49 ; EG-CHECK-LABEL: {{^}}store_i16:
    50 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
     50; EG-LABEL: {{^}}store_i16:
     51; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
    5152
    5253; IG 0: Get the byte index and truncate the value
    5354
    5455
    55 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
    56 ; EG-CHECK-NEXT: 3(4.203895e-45),
    57 
    58 ; EG-CHECK: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
    59 ; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
    60 
    61 ; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
     56; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
     57; EG-NEXT: 3(4.203895e-45),
     58
     59; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
     60; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
     61
     62; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
    6263; IG 1: Truncate the calculated the shift amount for the mask
    6364
    6465; IG 2: Shift the value and the mask
    65 ; EG-CHECK: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
    66 ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
    67 ; EG-CHECK-NEXT: 65535
     66; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
     67; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
     68; EG-NEXT: 65535
    6869; IG 3: Initialize the Y and Z channels to zero
    6970;       XXX: An optimal scheduler should merge this into one of the prevous IGs.
    70 ; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
    71 ; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
    72 
    73 ; SI-CHECK-LABEL: {{^}}store_i16:
    74 ; SI-CHECK: buffer_store_short
     71; EG: MOV T[[RW_GPR]].Y, 0.0
     72; EG: MOV * T[[RW_GPR]].Z, 0.0
     73
     74; SI-LABEL: {{^}}store_i16:
     75; SI: buffer_store_short
    7576define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
    7677entry:
     
    7980}
    8081
    81 ; EG-CHECK-LABEL: {{^}}store_v2i8:
    82 ; EG-CHECK: MEM_RAT MSKOR
    83 ; EG-CHECK-NOT: MEM_RAT MSKOR
    84 ; SI-CHECK-LABEL: {{^}}store_v2i8:
    85 ; SI-CHECK: buffer_store_byte
    86 ; SI-CHECK: buffer_store_byte
     82; EG-LABEL: {{^}}store_v2i8:
     83; EG: MEM_RAT MSKOR
     84; EG-NOT: MEM_RAT MSKOR
     85; SI-LABEL: {{^}}store_v2i8:
     86; SI: buffer_store_byte
     87; SI: buffer_store_byte
    8788define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
    8889entry:
     
    9394
    9495
    95 ; EG-CHECK-LABEL: {{^}}store_v2i16:
    96 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
    97 ; CM-CHECK-LABEL: {{^}}store_v2i16:
    98 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
    99 ; SI-CHECK-LABEL: {{^}}store_v2i16:
    100 ; SI-CHECK: buffer_store_short
    101 ; SI-CHECK: buffer_store_short
     96; EG-LABEL: {{^}}store_v2i16:
     97; EG: MEM_RAT_CACHELESS STORE_RAW
     98; CM-LABEL: {{^}}store_v2i16:
     99; CM: MEM_RAT_CACHELESS STORE_DWORD
     100; SI-LABEL: {{^}}store_v2i16:
     101; SI: buffer_store_short
     102; SI: buffer_store_short
    102103define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
    103104entry:
     
    107108}
    108109
    109 ; EG-CHECK-LABEL: {{^}}store_v4i8:
    110 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
    111 ; CM-CHECK-LABEL: {{^}}store_v4i8:
    112 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
    113 ; SI-CHECK-LABEL: {{^}}store_v4i8:
    114 ; SI-CHECK: buffer_store_byte
    115 ; SI-CHECK: buffer_store_byte
    116 ; SI-CHECK: buffer_store_byte
    117 ; SI-CHECK: buffer_store_byte
     110; EG-LABEL: {{^}}store_v4i8:
     111; EG: MEM_RAT_CACHELESS STORE_RAW
     112; CM-LABEL: {{^}}store_v4i8:
     113; CM: MEM_RAT_CACHELESS STORE_DWORD
     114; SI-LABEL: {{^}}store_v4i8:
     115; SI: buffer_store_byte
     116; SI: buffer_store_byte
     117; SI: buffer_store_byte
     118; SI: buffer_store_byte
    118119define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
    119120entry:
     
    124125
    125126; floating-point store
    126 ; EG-CHECK-LABEL: {{^}}store_f32:
    127 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
    128 ; CM-CHECK-LABEL: {{^}}store_f32:
    129 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
    130 ; SI-CHECK-LABEL: {{^}}store_f32:
    131 ; SI-CHECK: buffer_store_dword
     127; EG-LABEL: {{^}}store_f32:
     128; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
     129; CM-LABEL: {{^}}store_f32:
     130; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
     131; SI-LABEL: {{^}}store_f32:
     132; SI: buffer_store_dword
    132133
    133134define void @store_f32(float addrspace(1)* %out, float %in) {
     
    136137}
    137138
    138 ; EG-CHECK-LABEL: {{^}}store_v4i16:
    139 ; EG-CHECK: MEM_RAT MSKOR
    140 ; EG-CHECK: MEM_RAT MSKOR
    141 ; EG-CHECK: MEM_RAT MSKOR
    142 ; EG-CHECK: MEM_RAT MSKOR
    143 ; EG-CHECK-NOT: MEM_RAT MSKOR
    144 ; SI-CHECK-LABEL: {{^}}store_v4i16:
    145 ; SI-CHECK: buffer_store_short
    146 ; SI-CHECK: buffer_store_short
    147 ; SI-CHECK: buffer_store_short
    148 ; SI-CHECK: buffer_store_short
    149 ; SI-CHECK-NOT: buffer_store_byte
     139; EG-LABEL: {{^}}store_v4i16:
     140; EG: MEM_RAT MSKOR
     141; EG: MEM_RAT MSKOR
     142; EG: MEM_RAT MSKOR
     143; EG: MEM_RAT MSKOR
     144; EG-NOT: MEM_RAT MSKOR
     145; SI-LABEL: {{^}}store_v4i16:
     146; SI: buffer_store_short
     147; SI: buffer_store_short
     148; SI: buffer_store_short
     149; SI: buffer_store_short
     150; SI-NOT: buffer_store_byte
    150151define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
    151152entry:
     
    156157
    157158; vec2 floating-point stores
    158 ; EG-CHECK-LABEL: {{^}}store_v2f32:
    159 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
    160 ; CM-CHECK-LABEL: {{^}}store_v2f32:
    161 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
    162 ; SI-CHECK-LABEL: {{^}}store_v2f32:
    163 ; SI-CHECK: buffer_store_dwordx2
     159; EG-LABEL: {{^}}store_v2f32:
     160; EG: MEM_RAT_CACHELESS STORE_RAW
     161; CM-LABEL: {{^}}store_v2f32:
     162; CM: MEM_RAT_CACHELESS STORE_DWORD
     163; SI-LABEL: {{^}}store_v2f32:
     164; SI: buffer_store_dwordx2
    164165
    165166define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
     
    171172}
    172173
    173 ; EG-CHECK-LABEL: {{^}}store_v4i32:
    174 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
    175 ; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
    176 ; CM-CHECK-LABEL: {{^}}store_v4i32:
    177 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
    178 ; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
    179 ; SI-CHECK-LABEL: {{^}}store_v4i32:
    180 ; SI-CHECK: buffer_store_dwordx4
     174; EG-LABEL: {{^}}store_v4i32:
     175; EG: MEM_RAT_CACHELESS STORE_RAW
     176; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
     177; CM-LABEL: {{^}}store_v4i32:
     178; CM: MEM_RAT_CACHELESS STORE_DWORD
     179; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
     180; SI-LABEL: {{^}}store_v4i32:
     181; SI: buffer_store_dwordx4
    181182define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
    182183entry:
     
    186187
    187188; FUNC-LABEL: {{^}}store_i64_i8:
    188 ; EG-CHECK: MEM_RAT MSKOR
    189 ; SI-CHECK: buffer_store_byte
     189; EG: MEM_RAT MSKOR
     190; SI: buffer_store_byte
    190191define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) {
    191192entry:
     
    196197
    197198; FUNC-LABEL: {{^}}store_i64_i16:
    198 ; EG-CHECK: MEM_RAT MSKOR
    199 ; SI-CHECK: buffer_store_short
     199; EG: MEM_RAT MSKOR
     200; SI: buffer_store_short
    200201define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) {
    201202entry:
     
    210211
    211212; FUNC-LABEL: {{^}}store_local_i1:
    212 ; EG-CHECK: LDS_BYTE_WRITE
    213 ; SI-CHECK: ds_write_b8
     213; EG: LDS_BYTE_WRITE
     214; SI: ds_write_b8
    214215define void @store_local_i1(i1 addrspace(3)* %out) {
    215216entry:
     
    218219}
    219220
    220 ; EG-CHECK-LABEL: {{^}}store_local_i8:
    221 ; EG-CHECK: LDS_BYTE_WRITE
    222 ; SI-CHECK-LABEL: {{^}}store_local_i8:
    223 ; SI-CHECK: ds_write_b8
     221; EG-LABEL: {{^}}store_local_i8:
     222; EG: LDS_BYTE_WRITE
     223; SI-LABEL: {{^}}store_local_i8:
     224; SI: ds_write_b8
    224225define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
    225226  store i8 %in, i8 addrspace(3)* %out
     
    227228}
    228229
    229 ; EG-CHECK-LABEL: {{^}}store_local_i16:
    230 ; EG-CHECK: LDS_SHORT_WRITE
    231 ; SI-CHECK-LABEL: {{^}}store_local_i16:
    232 ; SI-CHECK: ds_write_b16
     230; EG-LABEL: {{^}}store_local_i16:
     231; EG: LDS_SHORT_WRITE
     232; SI-LABEL: {{^}}store_local_i16:
     233; SI: ds_write_b16
    233234define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
    234235  store i16 %in, i16 addrspace(3)* %out
     
    236237}
    237238
    238 ; EG-CHECK-LABEL: {{^}}store_local_v2i16:
    239 ; EG-CHECK: LDS_WRITE
    240 ; CM-CHECK-LABEL: {{^}}store_local_v2i16:
    241 ; CM-CHECK: LDS_WRITE
    242 ; SI-CHECK-LABEL: {{^}}store_local_v2i16:
    243 ; SI-CHECK: ds_write_b16
    244 ; SI-CHECK: ds_write_b16
     239; EG-LABEL: {{^}}store_local_v2i16:
     240; EG: LDS_WRITE
     241; CM-LABEL: {{^}}store_local_v2i16:
     242; CM: LDS_WRITE
     243; SI-LABEL: {{^}}store_local_v2i16:
     244; SI: ds_write_b16
     245; SI: ds_write_b16
    245246define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
    246247entry:
     
    249250}
    250251
    251 ; EG-CHECK-LABEL: {{^}}store_local_v4i8:
    252 ; EG-CHECK: LDS_WRITE
    253 ; CM-CHECK-LABEL: {{^}}store_local_v4i8:
    254 ; CM-CHECK: LDS_WRITE
    255 ; SI-CHECK-LABEL: {{^}}store_local_v4i8:
    256 ; SI-CHECK: ds_write_b8
    257 ; SI-CHECK: ds_write_b8
    258 ; SI-CHECK: ds_write_b8
    259 ; SI-CHECK: ds_write_b8
     252; EG-LABEL: {{^}}store_local_v4i8:
     253; EG: LDS_WRITE
     254; CM-LABEL: {{^}}store_local_v4i8:
     255; CM: LDS_WRITE
     256; SI-LABEL: {{^}}store_local_v4i8:
     257; SI: ds_write_b8
     258; SI: ds_write_b8
     259; SI: ds_write_b8
     260; SI: ds_write_b8
    260261define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) {
    261262entry:
     
    264265}
    265266
    266 ; EG-CHECK-LABEL: {{^}}store_local_v2i32:
    267 ; EG-CHECK: LDS_WRITE
    268 ; EG-CHECK: LDS_WRITE
    269 ; CM-CHECK-LABEL: {{^}}store_local_v2i32:
    270 ; CM-CHECK: LDS_WRITE
    271 ; CM-CHECK: LDS_WRITE
    272 ; SI-CHECK-LABEL: {{^}}store_local_v2i32:
    273 ; SI-CHECK: ds_write_b64
     267; EG-LABEL: {{^}}store_local_v2i32:
     268; EG: LDS_WRITE
     269; EG: LDS_WRITE
     270; CM-LABEL: {{^}}store_local_v2i32:
     271; CM: LDS_WRITE
     272; CM: LDS_WRITE
     273; SI-LABEL: {{^}}store_local_v2i32:
     274; SI: ds_write_b64
    274275define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
    275276entry:
     
    278279}
    279280
    280 ; EG-CHECK-LABEL: {{^}}store_local_v4i32:
    281 ; EG-CHECK: LDS_WRITE
    282 ; EG-CHECK: LDS_WRITE
    283 ; EG-CHECK: LDS_WRITE
    284 ; EG-CHECK: LDS_WRITE
    285 ; CM-CHECK-LABEL: {{^}}store_local_v4i32:
    286 ; CM-CHECK: LDS_WRITE
    287 ; CM-CHECK: LDS_WRITE
    288 ; CM-CHECK: LDS_WRITE
    289 ; CM-CHECK: LDS_WRITE
    290 ; SI-CHECK-LABEL: {{^}}store_local_v4i32:
    291 ; SI-CHECK: ds_write_b32
    292 ; SI-CHECK: ds_write_b32
    293 ; SI-CHECK: ds_write_b32
    294 ; SI-CHECK: ds_write_b32
     281; EG-LABEL: {{^}}store_local_v4i32:
     282; EG: LDS_WRITE
     283; EG: LDS_WRITE
     284; EG: LDS_WRITE
     285; EG: LDS_WRITE
     286; CM-LABEL: {{^}}store_local_v4i32:
     287; CM: LDS_WRITE
     288; CM: LDS_WRITE
     289; CM: LDS_WRITE
     290; CM: LDS_WRITE
     291; SI-LABEL: {{^}}store_local_v4i32:
     292; SI: ds_write_b32
     293; SI: ds_write_b32
     294; SI: ds_write_b32
     295; SI: ds_write_b32
    295296define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) {
    296297entry:
     
    300301
    301302; FUNC-LABEL: {{^}}store_local_i64_i8:
    302 ; EG-CHECK: LDS_BYTE_WRITE
    303 ; SI-CHECK: ds_write_b8
     303; EG: LDS_BYTE_WRITE
     304; SI: ds_write_b8
    304305define void @store_local_i64_i8(i8 addrspace(3)* %out, i64 %in) {
    305306entry:
     
    310311
    311312; FUNC-LABEL: {{^}}store_local_i64_i16:
    312 ; EG-CHECK: LDS_SHORT_WRITE
    313 ; SI-CHECK: ds_write_b16
     313; EG: LDS_SHORT_WRITE
     314; SI: ds_write_b16
    314315define void @store_local_i64_i16(i16 addrspace(3)* %out, i64 %in) {
    315316entry:
     
    326327; be two 32-bit stores.
    327328
    328 ; EG-CHECK-LABEL: {{^}}vecload2:
    329 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
    330 ; CM-CHECK-LABEL: {{^}}vecload2:
    331 ; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
    332 ; SI-CHECK-LABEL: {{^}}vecload2:
    333 ; SI-CHECK: buffer_store_dwordx2
     329; EG-LABEL: {{^}}vecload2:
     330; EG: MEM_RAT_CACHELESS STORE_RAW
     331; CM-LABEL: {{^}}vecload2:
     332; CM: MEM_RAT_CACHELESS STORE_DWORD
     333; SI-LABEL: {{^}}vecload2:
     334; SI: buffer_store_dwordx2
    334335define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
    335336entry:
     
    349350; FUNC-LABEL: {{^}}"i128-const-store":
    350351; FIXME: We should be able to to this with one store instruction
    351 ; EG-CHECK: STORE_RAW
    352 ; EG-CHECK: STORE_RAW
    353 ; EG-CHECK: STORE_RAW
    354 ; EG-CHECK: STORE_RAW
    355 ; CM-CHECK: STORE_DWORD
    356 ; CM-CHECK: STORE_DWORD
    357 ; CM-CHECK: STORE_DWORD
    358 ; CM-CHECK: STORE_DWORD
     352; EG: STORE_RAW
     353; EG: STORE_RAW
     354; EG: STORE_RAW
     355; EG: STORE_RAW
     356; CM: STORE_DWORD
     357; CM: STORE_DWORD
     358; CM: STORE_DWORD
     359; CM: STORE_DWORD
    359360; SI: buffer_store_dwordx2
    360361; SI: buffer_store_dwordx2
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