Ignore:
Timestamp:
Oct 16, 2015, 10:49:26 AM (4 years ago)
Author:
cameron
Message:

Encapsulation of bitblock and carry pack construction

File:
1 edited

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/icgrep/IDISA/idisa_builder.cpp

    r4827 r4837  
    1414
    1515Value * IDISA_Builder::bitBlockCast(Value * a) {
    16     return mLLVMBuilder->CreateBitCast(a, mBitBlockType);
     16    return a->getType() == mBitBlockType ? a : mLLVMBuilder->CreateBitCast(a, mBitBlockType);
    1717}
    1818
     
    2323
    2424Value * IDISA_Builder::fwCast(unsigned fw, Value * a) {
    25     return mLLVMBuilder->CreateBitCast(a, fwVectorType(fw));
     25    return a->getType() == fwVectorType(fw) ? a : mLLVMBuilder->CreateBitCast(a, fwVectorType(fw));
    2626}
    2727
    2828Value * IDISA_Builder::simd_add(unsigned fw, Value * a, Value * b) {
    29     return bitBlockCast(mLLVMBuilder->CreateAdd(fwCast(fw, a), fwCast(fw, b)));
     29    return mLLVMBuilder->CreateAdd(fwCast(fw, a), fwCast(fw, b));
    3030}
    3131
    3232Value * IDISA_Builder::simd_sub(unsigned fw, Value * a, Value * b) {
    33     return bitBlockCast(mLLVMBuilder->CreateSub(fwCast(fw, a), fwCast(fw, b)));
     33    return mLLVMBuilder->CreateSub(fwCast(fw, a), fwCast(fw, b));
    3434}
    3535
    3636Value * IDISA_Builder::simd_mult(unsigned fw, Value * a, Value * b) {
    37     return bitBlockCast(mLLVMBuilder->CreateMul(fwCast(fw, a), fwCast(fw, b)));
     37    return mLLVMBuilder->CreateMul(fwCast(fw, a), fwCast(fw, b));
    3838}
    3939
    4040Value * IDISA_Builder::simd_eq(unsigned fw, Value * a, Value * b) {
    41     return bitBlockCast(mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpEQ(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw)));
     41    return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpEQ(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    4242}
    4343
    4444Value * IDISA_Builder::simd_gt(unsigned fw, Value * a, Value * b) {
    45     return bitBlockCast(mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpSGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw)));
     45    return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpSGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    4646}
    4747
    4848Value * IDISA_Builder::simd_ugt(unsigned fw, Value * a, Value * b) {
    49     return bitBlockCast(mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpUGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw)));
     49    return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpUGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    5050}
    5151
    5252Value * IDISA_Builder::simd_lt(unsigned fw, Value * a, Value * b) {
    53     return bitBlockCast(mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpSLT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw)));
     53    return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpSLT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    5454}
    5555
    5656Value * IDISA_Builder::simd_ult(unsigned fw, Value * a, Value * b) {
    57     return bitBlockCast(mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpULT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw)));
     57    return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpULT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    5858}
    5959
     
    6161    Value * aVec = fwCast(fw, a);
    6262    Value * bVec = fwCast(fw, b);
    63     return bitBlockCast(mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpSGT(aVec, bVec), aVec, bVec));
     63    return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpSGT(aVec, bVec), aVec, bVec);
    6464}
    6565
     
    6767    Value * aVec = fwCast(fw, a);
    6868    Value * bVec = fwCast(fw, b);
    69     return bitBlockCast(mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpUGT(aVec, bVec), aVec, bVec));
     69    return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpUGT(aVec, bVec), aVec, bVec);
    7070}
    7171
     
    7373    Value * aVec = fwCast(fw, a);
    7474    Value * bVec = fwCast(fw, b);
    75     return bitBlockCast(mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpSLT(aVec, bVec), aVec, bVec));
     75    return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpSLT(aVec, bVec), aVec, bVec);
    7676}
    7777
     
    7979    Value * aVec = fwCast(fw, a);
    8080    Value * bVec = fwCast(fw, b);
    81     return bitBlockCast(mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpULT(aVec, bVec), aVec, bVec));
     81    return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpULT(aVec, bVec), aVec, bVec);
    8282}
    8383
    8484Value * IDISA_Builder::simd_slli(unsigned fw, Value * a, unsigned shift) {
    85     return bitBlockCast(mLLVMBuilder->CreateShl(fwCast(fw, a), shift));
     85    return mLLVMBuilder->CreateShl(fwCast(fw, a), shift);
    8686}
    8787
    8888Value * IDISA_Builder::simd_srli(unsigned fw, Value * a, unsigned shift) {
    89     return bitBlockCast(mLLVMBuilder->CreateLShr(fwCast(fw, a), shift));
     89    return mLLVMBuilder->CreateLShr(fwCast(fw, a), shift);
    9090}
    9191
    9292Value * IDISA_Builder::simd_srai(unsigned fw, Value * a, unsigned shift) {
    93     return bitBlockCast(mLLVMBuilder->CreateAShr(fwCast(fw, a), shift));
     93    return mLLVMBuilder->CreateAShr(fwCast(fw, a), shift);
    9494}
    9595
     
    9797    Value * cttzFunc = Intrinsic::getDeclaration(mMod, Intrinsic::cttz, fwVectorType(fw));
    9898    Value * rslt = mLLVMBuilder->CreateCall(cttzFunc, std::vector<Value *>({fwCast(fw, a), ConstantInt::get(mLLVMBuilder->getInt1Ty(), 0)}));
    99     return bitBlockCast(rslt);
     99    return rslt;
    100100}
    101101
     
    103103    Value * ctpopFunc = Intrinsic::getDeclaration(mMod, Intrinsic::ctpop, fwVectorType(fw));
    104104    Value * rslt = mLLVMBuilder->CreateCall(ctpopFunc, std::vector<Value *>({fwCast(fw, a)}));
    105     return bitBlockCast(rslt);
     105    return rslt;
    106106}
    107107
     
    115115        Idxs.push_back(mLLVMBuilder->getInt32(i + field_count)); // selects elements from second reg.
    116116    }
    117     return bitBlockCast(mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs)));
     117    return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    118118}
    119119
     
    127127        Idxs.push_back(mLLVMBuilder->getInt32(i + field_count)); // selects elements from second reg.
    128128    }
    129     return bitBlockCast(mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs)));
     129    return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    130130}
    131131
     
    138138        Idxs.push_back(mLLVMBuilder->getInt32(2*i));
    139139    }
    140     return bitBlockCast(mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs)));
     140    return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    141141}
    142142
     
    149149        Idxs.push_back(mLLVMBuilder->getInt32(2*i+1));
    150150    }
    151     return bitBlockCast(mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs)));
     151    return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    152152}
    153153
     
    170170        Idxs.push_back(mLLVMBuilder->getInt32(i));
    171171    }
    172     return bitBlockCast(mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs)));
     172    return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    173173}
    174174
     
    178178}
    179179
     180Value * IDISA_Builder::simd_and(Value * a, Value * b) {
     181    return a->getType() == b->getType() ? mLLVMBuilder->CreateAnd(a, b) : mLLVMBuilder->CreateAnd(bitBlockCast(a), bitBlockCast(b));
    180182}
     183
     184Value * IDISA_Builder::simd_or(Value * a, Value * b) {
     185    return a->getType() == b->getType() ? mLLVMBuilder->CreateOr(a, b) : mLLVMBuilder->CreateOr(bitBlockCast(a), bitBlockCast(b));
     186}
     187   
     188Value * IDISA_Builder::simd_xor(Value * a, Value * b) {
     189    return a->getType() == b->getType() ? mLLVMBuilder->CreateXor(a, b) : mLLVMBuilder->CreateXor(bitBlockCast(a), bitBlockCast(b));
     190}
     191
     192Value * IDISA_Builder::simd_not(Value * a) {
     193    return simd_xor(a, Constant::getAllOnesValue(a->getType()));
     194}
     195
     196}
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