Ignore:
Timestamp:
Dec 23, 2015, 11:47:47 AM (3 years ago)
Author:
cameron
Message:

Add IRBuilder functionality to IDISA_Builder; eliminate separate mBuilder

File:
1 edited

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/icgrep/IDISA/idisa_builder.cpp

    r4895 r4898  
    1515VectorType * IDISA_Builder::fwVectorType(unsigned fw) {
    1616    int fieldCount = mBitBlockWidth/fw;
    17     return VectorType::get(mLLVMBuilder->getIntNTy(fw), fieldCount);
     17    return VectorType::get(getIntNTy(fw), fieldCount);
    1818}
    1919
    2020Value * IDISA_Builder::fwCast(unsigned fw, Value * a) {
    21     return a->getType() == fwVectorType(fw) ? a : mLLVMBuilder->CreateBitCast(a, fwVectorType(fw));
     21    return a->getType() == fwVectorType(fw) ? a : CreateBitCast(a, fwVectorType(fw));
    2222}
    2323
     
    3232                                                   /*Linkage=*/ GlobalValue::PrivateLinkage,
    3333                                                   /*Initializer=*/ regNameData);
    34     Value * regStrPtr = mLLVMBuilder->CreateGEP(regStrVar, std::vector<Value *>({mLLVMBuilder->getInt64(0), mLLVMBuilder->getInt32(0)}));
    35     mLLVMBuilder->CreateCall(mPrintRegisterFunction, std::vector<Value *>({regStrPtr, bitCast(bitblockValue)}));
     34    Value * regStrPtr = CreateGEP(regStrVar, std::vector<Value *>({getInt64(0), getInt32(0)}));
     35    CreateCall(mPrintRegisterFunction, std::vector<Value *>({regStrPtr, bitCast(bitblockValue)}));
    3636}
    3737
    3838    Constant * IDISA_Builder::simd_himask(unsigned fw) {
    39         return Constant::getIntegerValue(mLLVMBuilder->getIntNTy(mBitBlockWidth), APInt::getSplat(mBitBlockWidth, APInt::getHighBitsSet(fw, fw/2)));
     39        return Constant::getIntegerValue(getIntNTy(mBitBlockWidth), APInt::getSplat(mBitBlockWidth, APInt::getHighBitsSet(fw, fw/2)));
    4040    }
    4141   
    4242    Constant * IDISA_Builder::simd_lomask(unsigned fw) {
    43         return Constant::getIntegerValue(mLLVMBuilder->getIntNTy(mBitBlockWidth), APInt::getSplat(mBitBlockWidth, APInt::getLowBitsSet(fw, fw/2)));
     43        return Constant::getIntegerValue(getIntNTy(mBitBlockWidth), APInt::getSplat(mBitBlockWidth, APInt::getLowBitsSet(fw, fw/2)));
    4444    }
    4545   
    4646    Value * IDISA_Builder::simd_add(unsigned fw, Value * a, Value * b) {
    47     return mLLVMBuilder->CreateAdd(fwCast(fw, a), fwCast(fw, b));
     47    return CreateAdd(fwCast(fw, a), fwCast(fw, b));
    4848}
    4949
    5050Value * IDISA_Builder::simd_sub(unsigned fw, Value * a, Value * b) {
    51     return mLLVMBuilder->CreateSub(fwCast(fw, a), fwCast(fw, b));
     51    return CreateSub(fwCast(fw, a), fwCast(fw, b));
    5252}
    5353
    5454Value * IDISA_Builder::simd_mult(unsigned fw, Value * a, Value * b) {
    55     return mLLVMBuilder->CreateMul(fwCast(fw, a), fwCast(fw, b));
     55    return CreateMul(fwCast(fw, a), fwCast(fw, b));
    5656}
    5757
    5858Value * IDISA_Builder::simd_eq(unsigned fw, Value * a, Value * b) {
    59     return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpEQ(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
     59    return CreateSExt(CreateICmpEQ(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    6060}
    6161
    6262Value * IDISA_Builder::simd_gt(unsigned fw, Value * a, Value * b) {
    63     return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpSGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
     63    return CreateSExt(CreateICmpSGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    6464}
    6565
    6666Value * IDISA_Builder::simd_ugt(unsigned fw, Value * a, Value * b) {
    67     return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpUGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
     67    return CreateSExt(CreateICmpUGT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    6868}
    6969
    7070Value * IDISA_Builder::simd_lt(unsigned fw, Value * a, Value * b) {
    71     return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpSLT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
     71    return CreateSExt(CreateICmpSLT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    7272}
    7373
    7474Value * IDISA_Builder::simd_ult(unsigned fw, Value * a, Value * b) {
    75     return mLLVMBuilder->CreateSExt(mLLVMBuilder->CreateICmpULT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
     75    return CreateSExt(CreateICmpULT(fwCast(fw, a), fwCast(fw, b)), fwVectorType(fw));
    7676}
    7777
     
    7979    Value * aVec = fwCast(fw, a);
    8080    Value * bVec = fwCast(fw, b);
    81     return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpSGT(aVec, bVec), aVec, bVec);
     81    return CreateSelect(CreateICmpSGT(aVec, bVec), aVec, bVec);
    8282}
    8383
     
    8585    Value * aVec = fwCast(fw, a);
    8686    Value * bVec = fwCast(fw, b);
    87     return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpUGT(aVec, bVec), aVec, bVec);
     87    return CreateSelect(CreateICmpUGT(aVec, bVec), aVec, bVec);
    8888}
    8989
     
    9191    Value * aVec = fwCast(fw, a);
    9292    Value * bVec = fwCast(fw, b);
    93     return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpSLT(aVec, bVec), aVec, bVec);
     93    return CreateSelect(CreateICmpSLT(aVec, bVec), aVec, bVec);
    9494}
    9595
     
    9797    Value * aVec = fwCast(fw, a);
    9898    Value * bVec = fwCast(fw, b);
    99     return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpULT(aVec, bVec), aVec, bVec);
     99    return CreateSelect(CreateICmpULT(aVec, bVec), aVec, bVec);
    100100}
    101101
    102102Value * IDISA_Builder::simd_slli(unsigned fw, Value * a, unsigned shift) {
    103     return mLLVMBuilder->CreateShl(fwCast(fw, a), shift);
     103    return CreateShl(fwCast(fw, a), shift);
    104104}
    105105
    106106Value * IDISA_Builder::simd_srli(unsigned fw, Value * a, unsigned shift) {
    107     return mLLVMBuilder->CreateLShr(fwCast(fw, a), shift);
     107    return CreateLShr(fwCast(fw, a), shift);
    108108}
    109109
    110110Value * IDISA_Builder::simd_srai(unsigned fw, Value * a, unsigned shift) {
    111     return mLLVMBuilder->CreateAShr(fwCast(fw, a), shift);
     111    return CreateAShr(fwCast(fw, a), shift);
    112112}
    113113
    114114Value * IDISA_Builder::simd_cttz(unsigned fw, Value * a) {
    115115    Value * cttzFunc = Intrinsic::getDeclaration(mMod, Intrinsic::cttz, fwVectorType(fw));
    116     Value * rslt = mLLVMBuilder->CreateCall(cttzFunc, std::vector<Value *>({fwCast(fw, a), ConstantInt::get(mLLVMBuilder->getInt1Ty(), 0)}));
     116    Value * rslt = CreateCall(cttzFunc, std::vector<Value *>({fwCast(fw, a), ConstantInt::get(getInt1Ty(), 0)}));
    117117    return rslt;
    118118}
     
    120120Value * IDISA_Builder::simd_popcount(unsigned fw, Value * a) {
    121121    Value * ctpopFunc = Intrinsic::getDeclaration(mMod, Intrinsic::ctpop, fwVectorType(fw));
    122     Value * rslt = mLLVMBuilder->CreateCall(ctpopFunc, std::vector<Value *>({fwCast(fw, a)}));
     122    Value * rslt = CreateCall(ctpopFunc, std::vector<Value *>({fwCast(fw, a)}));
    123123    return rslt;
    124124}
     
    127127    Value * aVec = fwCast(fw, a);
    128128    Value * bVec = fwCast(fw, b);
    129     return mLLVMBuilder->CreateSelect(mLLVMBuilder->CreateICmpSLT(cond, mZeroInitializer), aVec, bVec);
     129    return CreateSelect(CreateICmpSLT(cond, mZeroInitializer), aVec, bVec);
    130130}
    131131
     
    137137    std::vector<Constant*> Idxs;
    138138    for (unsigned i = field_count/2; i < field_count; i++) {
    139         Idxs.push_back(mLLVMBuilder->getInt32(i));    // selects elements from first reg.
    140         Idxs.push_back(mLLVMBuilder->getInt32(i + field_count)); // selects elements from second reg.
    141     }
    142     return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
     139        Idxs.push_back(getInt32(i));    // selects elements from first reg.
     140        Idxs.push_back(getInt32(i + field_count)); // selects elements from second reg.
     141    }
     142    return CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    143143}
    144144
     
    149149    std::vector<Constant*> Idxs;
    150150    for (unsigned i = 0; i < field_count/2; i++) {
    151         Idxs.push_back(mLLVMBuilder->getInt32(i));    // selects elements from first reg.
    152         Idxs.push_back(mLLVMBuilder->getInt32(i + field_count)); // selects elements from second reg.
    153     }
    154     return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
     151        Idxs.push_back(getInt32(i));    // selects elements from first reg.
     152        Idxs.push_back(getInt32(i + field_count)); // selects elements from second reg.
     153    }
     154    return CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    155155}
    156156
    157157Value * IDISA_Builder::esimd_bitspread(unsigned fw, Value * bitmask) {
    158158    unsigned field_count = mBitBlockWidth/fw;
    159     Type * field_type = mLLVMBuilder->getIntNTy(fw);
     159    Type * field_type = getIntNTy(fw);
    160160    if (bitmask->getType()->getIntegerBitWidth() < fw) {
    161         bitmask = mLLVMBuilder->CreateZExt(bitmask, field_type);
     161        bitmask = CreateZExt(bitmask, field_type);
    162162    }
    163163    else if (bitmask->getType()->getIntegerBitWidth() > fw) {
    164         bitmask = mLLVMBuilder->CreateTrunc(bitmask, field_type);
    165     }
    166     Value * spread_field = mLLVMBuilder->CreateBitCast(bitmask, VectorType::get(mLLVMBuilder->getIntNTy(fw), 1));
    167     Value * undefVec = UndefValue::get(VectorType::get(mLLVMBuilder->getIntNTy(fw), 1));
    168     Value * broadcast = mLLVMBuilder->CreateShuffleVector(spread_field, undefVec, Constant::getNullValue(VectorType::get(mLLVMBuilder->getInt32Ty(), field_count)));
     164        bitmask = CreateTrunc(bitmask, field_type);
     165    }
     166    Value * spread_field = CreateBitCast(bitmask, VectorType::get(getIntNTy(fw), 1));
     167    Value * undefVec = UndefValue::get(VectorType::get(getIntNTy(fw), 1));
     168    Value * broadcast = CreateShuffleVector(spread_field, undefVec, Constant::getNullValue(VectorType::get(getInt32Ty(), field_count)));
    169169    std::vector<Constant*> bitSel;
    170170    std::vector<Constant*> bitShift;
     
    175175    Value * bitSelVec = ConstantVector::get(bitSel);
    176176    Value * bitShiftVec = ConstantVector::get(bitShift);
    177     return mLLVMBuilder->CreateLShr(mLLVMBuilder->CreateAnd(bitSelVec, broadcast), bitShiftVec);
     177    return CreateLShr(CreateAnd(bitSelVec, broadcast), bitShiftVec);
    178178}
    179179
     
    184184    std::vector<Constant*> Idxs;
    185185    for (unsigned i = 0; i < field_count; i++) {
    186         Idxs.push_back(mLLVMBuilder->getInt32(2*i));
    187     }
    188     return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
     186        Idxs.push_back(getInt32(2*i));
     187    }
     188    return CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    189189}
    190190
     
    195195    std::vector<Constant*> Idxs;
    196196    for (unsigned i = 0; i < field_count; i++) {
    197         Idxs.push_back(mLLVMBuilder->getInt32(2*i+1));
    198     }
    199     return mLLVMBuilder->CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
     197        Idxs.push_back(getInt32(2*i+1));
     198    }
     199    return CreateShuffleVector(aVec, bVec, ConstantVector::get(Idxs));
    200200}
    201201
    202202Value * IDISA_Builder::hsimd_signmask(unsigned fw, Value * a) {
    203     Value * mask = mLLVMBuilder->CreateICmpSLT(fwCast(fw, a), ConstantAggregateZero::get(fwVectorType(fw)));
    204     return mLLVMBuilder->CreateZExt(mLLVMBuilder->CreateBitCast(mask, mLLVMBuilder->getIntNTy(mBitBlockWidth/fw)), mLLVMBuilder->getInt32Ty());
     203    Value * mask = CreateICmpSLT(fwCast(fw, a), ConstantAggregateZero::get(fwVectorType(fw)));
     204    return CreateZExt(CreateBitCast(mask, getIntNTy(mBitBlockWidth/fw)), getInt32Ty());
    205205}
    206206
    207207Value * IDISA_Builder::mvmd_extract(unsigned fw, Value * a, unsigned fieldIndex) {
    208208    Value * aVec = fwCast(fw, a);
    209     return mLLVMBuilder->CreateExtractElement(aVec, mLLVMBuilder->getInt32(fieldIndex));
     209    return CreateExtractElement(aVec, getInt32(fieldIndex));
    210210}
    211211
    212212Value * IDISA_Builder::mvmd_insert(unsigned fw, Value * blk, Value * elt, unsigned fieldIndex) {
    213213    Value * vec = fwCast(fw, blk);
    214     return mLLVMBuilder->CreateInsertElement(vec, elt, mLLVMBuilder->getInt32(fieldIndex));
     214    return CreateInsertElement(vec, elt, getInt32(fieldIndex));
    215215}
    216216
     
    221221    std::vector<Constant*> Idxs;
    222222    for (unsigned i = 0; i < field_count; i++) {
    223         Idxs.push_back(mLLVMBuilder->getInt32(i + shift));
    224     }
    225     return mLLVMBuilder->CreateShuffleVector(bVec, aVec, ConstantVector::get(Idxs));
     223        Idxs.push_back(getInt32(i + shift));
     224    }
     225    return CreateShuffleVector(bVec, aVec, ConstantVector::get(Idxs));
    226226}
    227227
    228228Value * IDISA_Builder::bitblock_any(Value * a) {
    229     Type * iBitBlock = mLLVMBuilder->getIntNTy(mBitBlockWidth);
    230     return mLLVMBuilder->CreateICmpNE(mLLVMBuilder->CreateBitCast(a, iBitBlock),  ConstantInt::get(iBitBlock, 0));
     229    Type * iBitBlock = getIntNTy(mBitBlockWidth);
     230    return CreateICmpNE(CreateBitCast(a, iBitBlock),  ConstantInt::get(iBitBlock, 0));
    231231}
    232232
    233233Value * IDISA_Builder::simd_and(Value * a, Value * b) {
    234     return a->getType() == b->getType() ? mLLVMBuilder->CreateAnd(a, b) : mLLVMBuilder->CreateAnd(bitCast(a), bitCast(b));
     234    return a->getType() == b->getType() ? CreateAnd(a, b) : CreateAnd(bitCast(a), bitCast(b));
    235235}
    236236
    237237Value * IDISA_Builder::simd_or(Value * a, Value * b) {
    238     return a->getType() == b->getType() ? mLLVMBuilder->CreateOr(a, b) : mLLVMBuilder->CreateOr(bitCast(a), bitCast(b));
     238    return a->getType() == b->getType() ? CreateOr(a, b) : CreateOr(bitCast(a), bitCast(b));
    239239}
    240240   
    241241Value * IDISA_Builder::simd_xor(Value * a, Value * b) {
    242     return a->getType() == b->getType() ? mLLVMBuilder->CreateXor(a, b) : mLLVMBuilder->CreateXor(bitCast(a), bitCast(b));
     242    return a->getType() == b->getType() ? CreateXor(a, b) : CreateXor(bitCast(a), bitCast(b));
    243243}
    244244
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