Ignore:
Timestamp:
Feb 16, 2017, 2:04:57 PM (2 years ago)
Author:
nmedfort
Message:

Attempt to diagnose / fix issue on jenkins server.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/icgrep/IR_Gen/idisa_target.cpp

    r5320 r5323  
    1111#include <IR_Gen/idisa_nvptx_builder.h>
    1212#include <llvm/IR/Module.h>
     13#ifndef NDEBUG
     14#include <llvm/ADT/Triple.h>
     15#endif
    1316
    1417namespace IDISA {
    1518   
    1619IDISA_Builder * GetIDISA_Builder(llvm::Module * mod) {
     20    if (LLVM_UNLIKELY(mod == nullptr)) {
     21        report_fatal_error("GetIDISA_Builder: module cannot be null");
     22    }
     23    if (LLVM_LIKELY(mod->getTargetTriple().empty())) {
     24        mod->setTargetTriple(llvm::sys::getProcessTriple());
     25    }
    1726    const bool hasAVX2 = AVX2_available();
    18     DataLayout DL(mod);
     27    DataLayout DL(mod);   
    1928    Type * const intTy = DL.getIntPtrType(mod->getContext());
    2029    const auto registerWidth = intTy->getIntegerBitWidth();
     30    #ifndef NDEBUG
     31    Triple T(mod->getTargetTriple());
     32    if (LLVM_UNLIKELY((T.isArch16Bit() && registerWidth != 16) || (T.isArch32Bit() && registerWidth != 32) || (T.isArch64Bit() && registerWidth != 64))) {
     33        report_fatal_error("GetIDISA_Builder: target triple '" + mod->getTargetTriple() + "' register width does not match data layout (" + std::to_string(registerWidth) + ")");
     34    }
     35    #endif
    2136    if (LLVM_LIKELY(codegen::BlockSize == 0)) {  // No BlockSize override: use processor SIMD width
    2237        codegen::BlockSize = hasAVX2 ? 256 : 128;
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