Ignore:
Timestamp:
Feb 16, 2017, 2:27:34 PM (2 years ago)
Author:
nmedfort
Message:

Attempt to diagnose / fix issue on jenkins server.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/icgrep/IR_Gen/idisa_target.cpp

    r5323 r5324  
    1111#include <IR_Gen/idisa_nvptx_builder.h>
    1212#include <llvm/IR/Module.h>
    13 #ifndef NDEBUG
    1413#include <llvm/ADT/Triple.h>
    15 #endif
    1614
    1715namespace IDISA {
     
    2422        mod->setTargetTriple(llvm::sys::getProcessTriple());
    2523    }
     24    Triple T(mod->getTargetTriple());
     25    unsigned registerWidth = 0;
     26    if (T.isArch64Bit()) {
     27        registerWidth = 64;
     28    } else if (T.isArch32Bit()) {
     29        registerWidth = 32;
     30    } else if (T.isArch16Bit()) {
     31        registerWidth = 16;
     32    }
    2633    const bool hasAVX2 = AVX2_available();
    27     DataLayout DL(mod);   
    28     Type * const intTy = DL.getIntPtrType(mod->getContext());
    29     const auto registerWidth = intTy->getIntegerBitWidth();
    30     #ifndef NDEBUG
    31     Triple T(mod->getTargetTriple());
    32     if (LLVM_UNLIKELY((T.isArch16Bit() && registerWidth != 16) || (T.isArch32Bit() && registerWidth != 32) || (T.isArch64Bit() && registerWidth != 64))) {
    33         report_fatal_error("GetIDISA_Builder: target triple '" + mod->getTargetTriple() + "' register width does not match data layout (" + std::to_string(registerWidth) + ")");
    34     }
    35     #endif
    3634    if (LLVM_LIKELY(codegen::BlockSize == 0)) {  // No BlockSize override: use processor SIMD width
    3735        codegen::BlockSize = hasAVX2 ? 256 : 128;
Note: See TracChangeset for help on using the changeset viewer.