Changeset 6109


Ignore:
Timestamp:
Jun 23, 2018, 11:42:42 AM (5 months ago)
Author:
cameron
Message:

IDISA progress

Location:
icGREP/icgrep-devel/icgrep/IR_Gen
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • icGREP/icgrep-devel/icgrep/IR_Gen/idisa_builder.cpp

    r6108 r6109  
    2020namespace IDISA {
    2121
    22 unsigned getVectorBitWidth(Value * vec) {
    23     return cast<VectorType>(vec->getType())->getBitWidth();
     22unsigned getVectorBitWidth(Value * a) {
     23    Type * aTy = a->getType();
     24    if (isa<IntegerType>(aTy)) return aTy->getPrimitiveSizeInBits();
     25    return cast<VectorType>(aTy)->getBitWidth();
    2426}
    2527   
     
    2931
    3032Value * IDISA_Builder::fwCast(const unsigned fw, Value * const a) {
    31     VectorType * const ty = fwVectorType(fw);
    32     assert (a->getType()->getPrimitiveSizeInBits() == ty->getPrimitiveSizeInBits());
    33     return CreateBitCast(a, ty);
     33    unsigned vecWidth = getVectorBitWidth(a);
     34    return CreateBitCast(a, VectorType::get(getIntNTy(fw), vecWidth / fw));
    3435}
    3536
     
    8788
    8889Constant * IDISA_Builder::simd_himask(unsigned fw) {
    89     return Constant::getIntegerValue(getIntNTy(mBitBlockWidth), APInt::getSplat(mBitBlockWidth, APInt::getHighBitsSet(fw, fw/2)));
     90    return ConstantVector::getSplat(mBitBlockWidth/fw, Constant::getIntegerValue(getIntNTy(fw), APInt::getHighBitsSet(fw, fw/2)));
    9091}
    9192
    9293Constant * IDISA_Builder::simd_lomask(unsigned fw) {
    93     return Constant::getIntegerValue(getIntNTy(mBitBlockWidth), APInt::getSplat(mBitBlockWidth, APInt::getLowBitsSet(fw, fw/2)));
     94    return ConstantVector::getSplat(mBitBlockWidth/fw, Constant::getIntegerValue(getIntNTy(fw), APInt::getLowBitsSet(fw, fw/2)));
    9495}
    9596
     
    276277        Type * const ty = shift->getType();
    277278        Value * const scaled = CreateMul(shift, ConstantInt::get(ty, fw));
    278         Value * const inbounds = CreateICmpULE(scaled, ConstantInt::get(ty, vecTy->getBitWidth()));
    279         CreateAssert(inbounds, "shift exceeds vector width");
     279        Value * const inbounds = CreateICmpULT(scaled, ConstantInt::get(ty, vecTy->getBitWidth()));
     280        CreateAssert(inbounds, "poison shift value: >= vector width");
    280281    }
    281282    value = CreateBitCast(value, intTy);
     
    304305        Type * const ty = shift->getType();
    305306        Value * const scaled = CreateMul(shift, ConstantInt::get(ty, fw));
    306         Value * const inbounds = CreateICmpULE(scaled, ConstantInt::get(ty, vecTy->getBitWidth()));
    307         CreateAssert(inbounds, "shift exceeds vector width");
     307        Value * const inbounds = CreateICmpULT(scaled, ConstantInt::get(ty, vecTy->getBitWidth()));
     308        CreateAssert(inbounds, "poison shift value: >= vector width");
    308309    }
    309310    value = CreateBitCast(value, intTy);
     
    412413                    simd_sllv(fw, simd_and(w, pext_shift_back_field_mask), pext_shift_back_amts));
    413414    }
    414     return CreateAnd(w, deposit_mask);
     415    return simd_and(w, deposit_mask);
    415416}
    416417
     
    476477   
    477478Value * IDISA_Builder::esimd_mergeh(unsigned fw, Value * a, Value * b) {
    478     if (getVectorBitWidth(a) > mBitBlockWidth) {
    479         Value * a_hi = CreateHalfVectorHigh(a);
    480         Value * b_hi = CreateHalfVectorHigh(b);
    481         return CreateDoubleVector(esimd_mergel(fw, a_hi, b_hi), esimd_mergeh(fw, a_hi, b_hi));
    482     }
    483     if (fw < 8) {
    484         Value * abh = simd_or(simd_and(simd_himask(fw*2), b), simd_srli(32, simd_and(simd_himask(fw*2), a), fw));
    485         Value * abl = simd_or(simd_slli(32, simd_and(simd_lomask(fw*2), b), fw), simd_and(simd_lomask(fw*2), a));
     479    if (fw < 8) {
     480        if (getVectorBitWidth(a) > mNativeBitBlockWidth) {
     481            Value * a_hi = CreateHalfVectorHigh(a);
     482            Value * b_hi = CreateHalfVectorHigh(b);
     483            return CreateDoubleVector(esimd_mergel(fw, a_hi, b_hi), esimd_mergeh(fw, a_hi, b_hi));
     484        }
     485        Value * abh = simd_or(simd_select_hi(fw*2, b), simd_srli(32, simd_select_hi(fw*2, a), fw));
     486        Value * abl = simd_or(simd_slli(32, simd_select_lo(fw*2, b), fw), simd_select_lo(fw*2, a));
    486487        return esimd_mergeh(fw * 2, abl, abh);
    487488    }
    488     const auto field_count = mBitBlockWidth / fw;
     489    const auto field_count = getVectorBitWidth(a) / fw;
    489490    Constant * Idxs[field_count];
    490491    for (unsigned i = 0; i < field_count / 2; i++) {
     
    496497
    497498Value * IDISA_Builder::esimd_mergel(unsigned fw, Value * a, Value * b) {
    498     if (getVectorBitWidth(a) > mBitBlockWidth) {
    499         Value * a_lo = CreateHalfVectorLow(a);
    500         Value * b_lo = CreateHalfVectorLow(b);
    501         return CreateDoubleVector(esimd_mergel(fw, a_lo, b_lo), esimd_mergeh(fw, a_lo, b_lo));
    502     }
    503     if (fw < 8) {
    504         Value * abh = simd_or(simd_and(simd_himask(fw*2), b), simd_srli(32, simd_and(simd_himask(fw*2), a), fw));
    505         Value * abl = simd_or(simd_slli(32, simd_and(simd_lomask(fw*2), b), fw), simd_and(simd_lomask(fw*2), a));
     499    if (fw < 8) {
     500        if (getVectorBitWidth(a) > mNativeBitBlockWidth) {
     501            Value * a_lo = CreateHalfVectorLow(a);
     502            Value * b_lo = CreateHalfVectorLow(b);
     503            return CreateDoubleVector(esimd_mergel(fw, a_lo, b_lo), esimd_mergeh(fw, a_lo, b_lo));
     504        }
     505        Value * abh = simd_or(simd_select_hi(fw*2, b), simd_srli(32, simd_select_hi(fw*2, a), fw));
     506        Value * abl = simd_or(simd_slli(32, simd_select_lo(fw*2, b), fw), simd_select_lo(fw*2, a));
    506507        return esimd_mergel(fw * 2, abl, abh);
    507508    }
    508     if (fw < 4) UnsupportedFieldWidthError(fw, "mergel");
    509     const auto field_count = mBitBlockWidth / fw;
     509    const auto field_count = getVectorBitWidth(a) / fw;
    510510    Constant * Idxs[field_count];
    511511    for (unsigned i = 0; i < field_count / 2; i++) {
     
    817817}
    818818
    819 
    820819Constant * IDISA_Builder::bit_interleave_byteshuffle_table(unsigned fw) {
    821     const unsigned fieldCount = mBitBlockWidth/8;
     820    const unsigned fieldCount = mNativeBitBlockWidth/8;
    822821    if (fw > 2) llvm::report_fatal_error("bit_interleave_byteshuffle_table requires fw == 1 or fw == 2");
    823822    // Bit interleave using shuffle.
     
    833832}
    834833
    835 
    836834IDISA_Builder::IDISA_Builder(LLVMContext & C, unsigned nativeVectorWidth, unsigned vectorWidth, unsigned laneWidth)
    837835: CBuilder(C)
  • icGREP/icgrep-devel/icgrep/IR_Gen/idisa_builder.h

    r6108 r6109  
    5050   
    5151    llvm::Value * bitCast(llvm::Value * a) {
    52         return CreateBitCast(a, mBitBlockType);
     52        return fwCast(mLaneWidth, a);
    5353    }
    5454
Note: See TracChangeset for help on using the changeset viewer.