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Timestamp:
Mar 16, 2011, 5:50:31 PM (9 years ago)
Author:
lindanl
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more outline on paper

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  • docs/PACT2011/04-methodology.tex

    r927 r949  
    11\section{Methodology}
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     3
    24In this section, we describe our methodology for the measurements and investigation of XML parsing energy consumption and performance. In brief, for each of the XML parsers under study we propose to measure and evaluate the energy consumption required to carry out XML well-formedness checking, under a variety of workloads, and as executed on both mobile device and server hardware.
    35
    46To begin our study, we propose to first investigate each of the XML parsers in terms of the PMCs hardware events as listed in the following subsection. Based on previous key works \cite{bellosa2001, bertran2010, bircher2007}, we have chosen several key hardware performance events for which the authors indicate have a strong correlation to energy consumption. From these data, we hope to gain insight into the XML parser execution characteristics which most significantly contribute to overall energy consumption. Secondly, using the Fluke i410 current clamp meter, we plan to measure the total energy consumption required to complete XML well-formedness checking for each XML parser, on each hardware platform, and for each of a number of XML source files.
     7
     8The foundational work by Bellosa in \cite{bellosa2001} as well as more recent work in \cite {bircher2007, bertran2010}
     9show that hardware-usage patterns has a significant impact in the energy consumption of a particular application;
     10\cite{bellosa2001, bircher2007, bertran2010} further show that there is a strong correlation between
     11specific performance events and energy usage---but the authors of each differ slightly in opinion as to
     12which performance monitoring counters\footnote{Performance monitoring counters (PMCs) are special-purpose registers that are included in most modern microprocessors;
     13they store the running count of specific hardware events, such as retired instructions, cache misses, branch mispredictions, and arithmetic-logic unit operations to name a few.
     14They can be used to capture information about any program at run-time, under any workload, at a very fine granularity.} (PMCs) to use.
     15
     16
    517
    618% The use of performance counters for modeling power is not a new concept.
     
    1325
    1426\subsection{Parsers}\label{parsers}
     27
    1528The XML parsing technologies selected for this study are the Parabix2, Xerces-C++, and Expat XML parsers.
    1629Parabix2 \cite{parabix2} (parallel bit streams for XML) is the second generation Parabix parser. Parabix2 is an open-source XML parser that leverages the SIMD capabilities of modern commodity processors; it employs the new parallelization techniques using parallel parsing with bit stream addition to deliver dramatic performance improvements over traditional byte-at-a-time parsing technology.
     
    4457systems as well as an open interchange format for geographic transactions on the Internet.
    4558The po.xml file is an example of purchase order data, while the soap.xml file contains a large SOAP message.
    46 This markup density metric is reported for each document.\cite{CameronHerdyLin2008}
     59This markup density metric is reported for each
     60document.\cite{CameronHerdyLin2008}
    4761
     62Describe parameters; what each parameter means.
    4863\subsection{Platform Hardware}
    49 \subsubsection{Mobile - ARM}
    50 The Advanced RISC Machine (ARM) is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings.
    51 ARM processors are used extensively in mobile phones. About 98 percent of the more than one billion mobile phones sold on 2005 use at least one ARM processor \cite{arm}.
    52 Table \ref{arm} gives the hardware description of the ARM based Samsung Galaxy Tablet selected.
    53 \begin{table}
    54 \begin{center}
    55 \begin{tabular}{|c||c|}
    56 \hline
    57 Processor & ARM Cortex-A8 (1.0GHz) \\ \hline
    58 L1 Cache & 32KB I-Cache, 32K D-Cache \\ \hline
    59 L2 Cache &  TBD\\ \hline
    60 Memory & 512M   \\ \hline       
    61 Storage & 16G \\ \hline
    6264
    63 \end{tabular}
    64 \end{center}
    65 \caption{Samsung Galaxy Tablet}
    66 \label{arm}
    67 \end{table}
    6865
    6966\subsubsection{Server - Intel Core i3}
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