Ignore:
Timestamp:
Mar 16, 2011, 5:50:31 PM (9 years ago)
Author:
lindanl
Message:

more outline on paper

File:
1 edited

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  • docs/PACT2011/05-performance.tex

    r927 r949  
    11\section{Performance Characteristic}
    22\subsection{Cache behavior}
     3
     4\begin{figure}
     5\begin{center}
     6\includegraphics[width=100mm]{figures/corei3_L1DM.pdf}
     7\end{center}
     8\caption{L1 Data Cache Misses/ KB on core i3}
     9\label{corei3_L1DM}
     10\end{figure}
     11
     12\begin{figure}
     13\begin{center}
     14\includegraphics[width=100mm]{figures/corei3_L2DM.pdf}
     15\end{center}
     16\caption{L2 Data Cache Misses/ KB on core i3}
     17\label{corei3_L2DM}
     18\end{figure}
     19
     20\begin{figure}
     21\begin{center}
     22\includegraphics[width=100mm]{figures/corei3_L3CM.pdf}
     23\end{center}
     24\caption{L3 Cache Misses/ KB on core i3}
     25\label{corei3_L3TM}
     26\end{figure}
     27
    328\subsection{SIMD/Total Instructions}
     29
     30\begin{figure}
     31\begin{center}
     32\includegraphics[width=100mm]{figures/corei3_INS.pdf}
     33\end{center}
     34\caption{Vector instruction vs. non-vertor instruction on core i3}
     35\label{corei3_INS}
     36\end{figure}
     37
    438\subsection{*SIMD/Total Loads}
    539\subsection{Branch Mispredictions}
     40\begin{figure}
     41\begin{center}
     42\includegraphics[width=100mm]{figures/corei3_BM.pdf}
     43\end{center}
     44\caption{Branch Mispredictions/ KB on core i3}
     45\label{corei3_BM}
     46\end{figure}
    647\subsection{CPU Cycles}
     48\begin{figure}
     49\begin{center}
     50\includegraphics[width=100mm]{figures/corei3_TOT.pdf}
     51\end{center}
     52\caption{Total CPU Cycles/ KB on core i3}
     53\label{corei3_TOT}
     54\end{figure}
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