Changeset 954 for docs/PACT2011


Ignore:
Timestamp:
Mar 18, 2011, 1:30:24 PM (9 years ago)
Author:
lindanl
Message:

Add more charts, modified abstract and some other minor changes

Location:
docs/PACT2011
Files:
2 added
1 deleted
5 edited

Legend:

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  • docs/PACT2011/00-abstract.tex

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    1 XML is a data format designed for documents as well as the representation of data structures.
    2 The simplicity and generality of the rules make it widely used in web services and database systems.
    3 Traditional byte-at-a time XML parsers have reach their bottleneck for further improvement to satisfy the growing demand on high performance and energy efficient XML parsing.
    4 We propose a new XML parser, Parabix, based on parallel bit stream technology, which enables parallel processing using SIMD registers.
    5 We evaluate and analyze the characteristic of our first and second version parsers, which is later referred as Parabix1 and Parabix2,
    6 as well as two other popular XML parsers, Expat and Xerces on three generations of x86 machines, Dual Core, Core i3 and Sandy Bridge.
    7 The results show that Parabix2 runs 2X to 8X faster than Expat and Xerces and performs much better in terms of data cache misses and branch misperditions.
    8 Moreover, Parabix2 scales better on the three different architectures and achieves more performance improvement on newer ones.
    9 With the same level of power consumption of all parsers we studied, Parabix2 consumes much less energy.
     1XML is a data format designed for documents as well as the
     2representation of data structures. The simplicity and generality of
     3the rules make it widely used in web services and database
     4systems. Traditional XML parsers have been built around the
     5byte-at-a-time model, in which they process every character token in
     6the file in a sequential fashion. Unfortunately, the byte-at-time
     7sequential model is a fundamental hindrance on performance and and in
     8some cases can add up 100\% overhead to the database queries
     9themselves.
     10
     11In this paper, we propose a new XML parser, Parabix, based on parallel
     12bit stream technology, which converts the character strings into
     13bitstreams and then exploits SIMD operations prevalent on modern CPUs.
     14The first generation parser that we developed, Parabix1, uses the
     15bitscan and bitlevel sequencing SIMD operations to emulate much of the
     16parsers functions. Unfortunately operations like bitscan are
     17inherently sequential nature and Parabix1's speedup is limited. We
     18present a second generation parser, Parabix2, that fully parallelizes
     19the parsing operations using using parallel bitlevel logic provided in
     20modern SIMD extensions like SSE2.  We evaluate Parabix1and Parabix2
     21against two widely-used XML parsers, Apache's Expat and IBM's Xerces
     22on three generations of x86 machines, including the new Intel
     23Sandybridge. We show that Parabix2's speedup is 2$\times$---8$\times$
     24over Expat and Xerces. Across the different Intel machine generations,
     25Parabix rides the scalability curve of SIMD operations whose
     26performance inherently scales better than traditional sequential
     27thread performance. Comparing Intel's new Sandbrige core with the Core
     28i3 we observed performance improvement between 20---60\% for our
     29Parabix parsers while sequential parsers like Xerces improve by
     30$<$20\%. We measure real CPU power to demonstrate that Parabix also
     31brings with itself significant energy efficiency. On the core i3,
     32Parabix consumes $\simeq$4nJ per byte parsed while Xerces consumes
     33$\simeq$20nJ per byte parsed. Finally, we perform a case study of the
     34Intel's new 256-bit wide AVX instructions, and demonstrate that it
     35provides X speedup over 128 bit SSE2 instruction set.
     36
  • docs/PACT2011/03-research.tex

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    1 \section{Parabix1}
     1\section{Parabix}
    22\label{section:reserach}
    33Describe key technology behind Parabix
  • docs/PACT2011/04-methodology.tex

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    6262Describe parameters; what each parameter means.
    6363\subsection{Platform Hardware}
     64\subsubsection{Intel Core 2}
     65\begin{table}[h]
     66\begin{center}
     67\begin{tabular}{|c||c|}
     68\hline
     69Processor & Core(TM)2 6400  (2.13GHz) \\ \hline
     70L1 Cache & 32KB I-Cache, 32KB D-Cache \\ \hline
     71L2 Cache & 2MB \\ \hline
     72Front Side Bus & 1333 MHz \\ \hline
     73Memory  & 2GB \\ \hline
    6474
    65 
    66 \subsubsection{Server - Intel Core i3}
     75\end{tabular}
     76\end{center}
     77\caption{Core 2}
     78\label{core2}
     79\end{table}
     80\subsubsection{Intel Core i3}
    6781The Intel Core i3 is a Nehalem based processor produced by Intel. The intent of this processor is to serve as a
    6882low end server processor. Table \ref{i3} gives the hardware description of the Intel Core i3 based machine selected.
     
    86100\end{table}
    87101
    88 \subsubsection{Server - Sandy Bridge}
     102\subsubsection{Sandy Bridge}
    89103
    90104\subsection{PMC Hardware Events}\label{events}
  • docs/PACT2011/05-performance.tex

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    3030\begin{figure}
    3131\begin{center}
    32 \includegraphics[width=85mm]{plots/corei3_INS.pdf}
     32\includegraphics[width=85mm]{plots/corei3_INS_p1.pdf}
    3333\end{center}
    34 \caption{Vector instruction vs. non-vertor instruction on core i3}
    35 \label{corei3_INS}
     34\caption{Vector instruction vs. non-vertor instruction for Parabix1 on core i3}
     35\label{corei3_INS_p1}
     36\end{figure}
     37
     38\begin{figure}
     39\begin{center}
     40\includegraphics[width=85mm]{plots/corei3_INS_p2.pdf}
     41\end{center}
     42\caption{Vector instruction vs. non-vertor instruction for Parabix2 on core i3}
     43\label{corei3_INS_p2}
    3644\end{figure}
    3745
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