Changeset 983

Mar 23, 2011, 8:21:45 PM (8 years ago)

section 7

1 edited


  • docs/PACT2011/07-avx.tex

    r975 r983  
     3In this section, we briefly highlight the improvements made in the Advanced Vector Extensions (AVX) extension to the x86 instruction set architecture and discuss the impact of these improvements on Parabix2. As neither Expat nor Xerces-C benefit from AVX, we do not discuss them in this section.
     4%The results of our experiments with the AVX and Sandy Bridge architecture can be seen in Figure \ref{avx}.
     6% Following AMD's announcement of their SSE5 architecture, Intel announced their intention to develop the AVX
    1116\subsection{Three Operand Form}
    13 \subsection{256 bits Operations}
     18Originally, SIMD SSE instructions operated using a two-operand form. This meant that given any SIMD instruction $a~\texttt{[op]}~b$ the result of that instruction would replace the value of $a$ or $b$ with the result. Thus whenever the subsequent instructions used the value of both $a$ and $b$, one of them had to be either reconstructed, or an additional store and load operation was required to recover that value. Utilizing the new VEX instruction coding scheme \textbf{[citation needed]}, Intel now allows the use of non-destructive three-operand operations in their SSE and AVX instruction sets. As shown in Figure \ref{avx}, simply enabling three-operand form on the existing 128-bit SSE instructions reduced the overall cycle count by between 11.7\% and 13.5\%. While this is a one-time savings, it provided a significant performance improvement that traditional parsers cannot leverage.
     20\subsection{256-bit Operations}
     22Although the AVX instruction set provided on the Sandy Bridge allows the use of 256-bit SIMD registers, Intel focused on implementing floating point operations as opposed to the integer based operations. This proved to be a significant challenge when porting Parabix2 from the 128-bit SSE to the 256-bit AVX instruction set. Even though we forsaw a gain in terms of memory throughput, many of the 128-bit SSE instructions used in Parabix2 did not have a corresponding 256-bit AVX instruction. Bitwise logic, which represented $30\%$ of the executed instructions in our test cases \textbf{[need more accurate figures here]}, was directly ported into pure AVX. The remaining $70\%$ of the instructions had to be simulated by breaking the 256-bit register into two 128-bit registers, performing the SSE version of the operation on both registers then combining the results back into the 256-bit register. As Figure \ref{avx} shows, this resulted in only a 0.4\% improvement in the case of dew.xml---which had the lowest markup density and therefore executed the fewest simulated 256-bit instructions---over the three-operand SSE implementation but incurred a performance penalty in the other four test cases. We expect that we could gain a significant performance improvement if future implementations of AVX incorporated integer-based shift and arithmetic operations. %Additionally, if we could efficiently switch between two- and three-operand form
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