Version 9 (modified by cameron, 5 years ago) (diff) |
---|

# The Complete Integer Project

This project involves systematic support for integers and vectors of integers in all power-of-2 configurations up to N bits, where N = 256 (or possibly 512 or 1024).

In general, this project seeks to "fill in the gaps" of LLVM support, specifically as follows.

- Add first class support for short integer types i1, i2, i4.
- Add first class support for LongInteger types i128, ...
- Add first class support for vectors of integers of i1, i2 and i4 types up to <N x i1>, <N/2 x i2>, <N/4 x i4>.
- Add first class support for vectors of long integers <N/128 x i128>, ...

## include/llvm/CodeGen/ValueTypes.h

This file has the complete list of types "that is supported natively by some processor targeted by LLVM". At present it includes some of the types (notably 32xi1 and 64xi1) targeted by the project, but lacks many as well. This file and include/llvm/CodeGen/ValueTypes.Td need to be updated with the complete set.

## Short Integer Types

Should the i1, i2, i4 types be legalized? They seem to arise in some SIMD operations such as the natural bitcast from <2 x i1> to i2.

The I2Result bug needs to be addressed.

Vectors of short integers may be more important than the short integers themselves.

## Long Integer Project

Parabix applications need long stream addition, subtraction and shift operations. There are standard ways of implementing these, including our parallel long-stream addition algorithm. Can these be integrated into LLVM?

The LongInteger project involves systematic support of the i256 type on LLVM, taking advantage of AVX2 instructions on the latest Intel Haswell chips.

## Vectors of Short Integers

The types <32 x i1> and <64 x i1> are particularly important to legalize, so that the BitShuffle subproject can be implemented.

### Example: 2-bit Fields

There can be some applications of 2-bit integer fields, i.e., the SIMD vector type <64 x i2> for 128-bit SIMD registers.

Can this be implemented in a generic way as follows:

- Make it a legal type in the SelectionDAG LegalizeTypes phase.
- Create implementations of the standard vector operations and rule out all others in the SelectionDAG Legalize phase.
- Implement each operation using bitwise logic on the 2 positions of each field.

We explore this possibility with the i2Vector project.

### Type Legalization

#### !X86/X86ISelLowering.cpp

New `addRegisterClass` statements required.

The `i1` vector types.

addRegisterClass(MVT::v32i1, &X86::GR32RegClass); addRegisterClass(MVT::v64i1, &X86::GR64RegClass); addRegisterClass(MVT::v128i1, &X86::VR128RegClass); addRegisterClass(MVT::v256i1, &X86::VR256RegClass); addRegisterClass(MVT::v512i1, &X86::VR512RegClass);

The `i2` vector types.

addRegisterClass(MVT::v16i2, &X86::GR32RegClass); addRegisterClass(MVT::v32i2, &X86::GR64RegClass); addRegisterClass(MVT::v64i2, &X86::VR128RegClass); addRegisterClass(MVT::v128i2, &X86::VR256RegClass); addRegisterClass(MVT::v256i2, &X86::VR512RegClass);

The `i4` vector types.

addRegisterClass(MVT::v8i4, &X86::GR32RegClass); addRegisterClass(MVT::v16i4, &X86::GR64RegClass); addRegisterClass(MVT::v32i4, &X86::VR128RegClass); addRegisterClass(MVT::v64i4, &X86::VR256RegClass); addRegisterClass(MVT::v128i4, &X86::VR512RegClass);

Additional vector types.

addRegisterClass(MVT::v4i8, &X86::GR32RegClass); addRegisterClass(MVT::v2i16, &X86::GR32RegClass); addRegisterClass(MVT::v8i8, &X86::GR64RegClass); addRegisterClass(MVT::v4i16, &X86::GR64RegClass); addRegisterClass(MVT::v2i32, &X86::GR64RegClass);

## Vectors of Long Integers

Right now, this seems like the least important of the subjprojects here, but is included for completeness.