Changes between Version 1 and Version 2 of IDISAproject


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Timestamp:
May 5, 2010, 6:04:44 AM (9 years ago)
Author:
cameron
Comment:

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  • IDISAproject

    v1 v2  
    7676The project has the following components.
    7777
    78  1.  IDISA generator kit.
    79     The IDISA generator kit is used to generate IDISA
    80     implementations for given source language/compiler/architecture
    81     combinations.   For example, we could generate an IDISA
    82     language consist of a C library using GCC vector conventions
    83     for the Power PC Altivec instruction set, or a C++ library
    84     using MSVC conventions for the Intel SSE2 instruction set.
    85     However, it should also have the flexibility for non-SIMD implementations
    86     such as implementation of a Python library using Python
    87     conventions for operations on unbounded bitstreams.
     78=== IDISA Generator Kit ===
     79The IDISA generator kit is used to generate IDISA
     80implementations for given source language/compiler/architecture
     81combinations.   For example, we could generate an IDISA
     82language consist of a C library using GCC vector conventions
     83for the Power PC Altivec instruction set, or a C++ library
     84using MSVC conventions for the Intel SSE2 instruction set.
     85However, it should also have the flexibility for non-SIMD implementations
     86such as implementation of a Python library using Python
     87conventions for operations on unbounded bitstreams.
    8888
    89     The generator kit should include optimization technology to
    90     ensure that the best possible IDISA implementation is realized for
    91     any given platform.
     89The generator kit should include optimization technology to
     90ensure that the best possible IDISA implementation is realized for
     91any given platform.
    9292
    93  1.  IDISA test generator.
    94     The test generator complements the generator kit by producing
    95     a comprehensive test suite for correctness testing of IDISA
    96     implementations.
     93=== IDISA Test Generator ===
     94The test generator complements the generator kit by producing
     95a comprehensive test suite for correctness testing of IDISA
     96implementations.
    9797
    98  1. IDISA compile-time specialization kit.   The compile-time
    99     specialization kit is used to provide optimized implementations
    100     of IDISA under known static properties of operand values.
    101     For example, if it is known that the high bit of each 4-bit
    102     field in registers $a$ an $b$ is zero, then a simd<4>::add(a,b)
    103     operation with no direct implementation on a particular
    104     platform can be realized by a wider-width operation that is,
    105     such as simd<16>::add(a,b) on most platforms.
     98=== IDISA Compile-Time Specialization Kit ===
    10699
    107  1.  IDISA reverse instruction optimizer.   Various processor
    108     architectures provide combined SIMD operations that correspond
    109     to sequences of IDISA instructions.  For example, the Intel
    110     PSADBW performs a packed sum of absolute differences corresponding
    111     to the following 5 IDISA operations.
    112          t1 = simd<8>::abs(simd<8>::sub(a,b))
    113          psadbw = simd<64>::add(simd<32>::add(simd<16>::add(t1)))
    114     The reverse instruction optimizer uses knowledge of these
    115     available optimized forms to generate optimized implementations
    116     where appropriate IDISA instruction sequences may be found.
    117     Note that the recognition may involve special case logic:
    118     psadbw can be efficiently used for the 8-field horizontal
    119     addition: simd<64>::add(simd<32>::add(simd<16>::add(x)))
    120     using psadbw(x, 0).
     100The compile-time
     101specialization kit is used to provide optimized implementations
     102of IDISA under known static properties of operand values.
     103For example, if it is known that the high bit of each 4-bit
     104field in registers a and b is zero, then a simd<4>::add(a,b)
     105operation with no direct implementation on a particular
     106platform can be realized by a wider-width operation that is,
     107such as simd<16>::add(a,b) on most platforms.
     108
     109=== IDISA Reverse Instruction Optimizer. ===
     110Various processor
     111architectures provide combined SIMD operations that correspond
     112to sequences of IDISA instructions.  For example, the Intel
     113PSADBW performs a packed sum of absolute differences corresponding
     114to the following 5 IDISA operations.
     115  t1 = simd<8>::abs(simd<8>::sub(a,b))[[BR]]
     116  psadbw = simd<64>::add(simd<32>::add(simd<16>::add(t1)))[[BR]]
     117The reverse instruction optimizer uses knowledge of these
     118available optimized forms to generate optimized implementations
     119where appropriate IDISA instruction sequences may be found.
     120Note that the recognition may involve special case logic:
     121psadbw can be efficiently used for the 8-field horizontal
     122addition: simd<64>::add(simd<32>::add(simd<16>::add(x)))
     123using psadbw(x, 0).