Changes between Version 4 and Version 5 of SSE2_Hoisting


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Timestamp:
Apr 14, 2014, 5:03:33 PM (4 years ago)
Author:
cameron
Comment:

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  • SSE2_Hoisting

    v4 v5  
    4040
    4141    a.  In each case that an SSE2 intrinsic requires a sequence of LLVM operations (excluding bitcasts and constants), ensure that SSE2 code generation recognizes the transformed sequence to allow the single intrinsic to be produced during code generation.
    42 
    4342    a.  Modify the code generator for at least one other target to recognize sequences produces by SSE2 hoisting and generate efficient code based on that recognition.
    4443
     
    6059versions.
    6160
    62     a.  The result of the hoisted code compiled with SSE2/x86-64 as the target SIMD architecture.
    63 
    64     a.  The result of the hoisted code compiled with a later SIMD ISA on x86-64 architecture.
    65 
    66     a.  The result of the hoisted code complied with non x86 architecture, such as ARM with Neon SIMD instructions.
     61  a.  The result of the hoisted code compiled with SSE2/x86-64 as the target SIMD architecture.
     62  a.  The result of the hoisted code compiled with a later SIMD ISA on x86-64 architecture.
     63  a.  The result of the hoisted code complied with non x86 architecture, such as ARM with Neon SIMD instructions.
    6764
    6865