Changes between Version 9 and Version 10 of ShuffleVector


Ignore:
Timestamp:
Apr 26, 2014, 6:58:41 PM (5 years ago)
Author:
cameron
Comment:

--

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  • ShuffleVector

    v9 v10  
    3131these special cases?
    3232
     33The [wiki:ShufflePatternLibrary Shuffle Pattern Library] attempts to do this.
     34
    3335== Lai ShengZhang's !GitHub ==
    3436
     
    4648See the BitShuffle subproject.
    4749
    48 == LLVM Source Code and Shuffles ==
    49 
    50 The following grep results show shuffle occurring throughout the LLVM code base in all kinds of special cases.
    51 {{{
    52 include/llvm-c/Core.h:  LLVMShuffleVector  = 52,
    53 include/llvm-c/Core.h:      macro(ShuffleVectorInst)              \
    54 include/llvm-c/Core.h:LLVMValueRef LLVMConstShuffleVector(LLVMValueRef VectorAConstant,
    55 include/llvm-c/Core.h:LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef, LLVMValueRef V1,
    56 lib/Analysis/ConstantFolding.cpp:  case Instruction::ShuffleVector:
    57 lib/Analysis/ConstantFolding.cpp:    return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]);
    58 lib/Analysis/CostModel.cpp:static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
    59 lib/Analysis/CostModel.cpp:  // We don't need a shuffle if we just want to have element 0 in position 0 of
    60 lib/Analysis/CostModel.cpp:  SmallVector<int, 16> ActualMask = SI->getShuffleMask();
    61 lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
    62 lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
    63 lib/Analysis/CostModel.cpp:  ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(L);
    64 lib/Analysis/CostModel.cpp:  ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(R);
    65 lib/Analysis/CostModel.cpp:  // On level 0 we can omit one shufflevector instruction.
    66 lib/Analysis/CostModel.cpp:  // Shuffle inputs must match.
    67 lib/Analysis/CostModel.cpp:    // If we have two shuffles their operands must match.
    68 lib/Analysis/CostModel.cpp:    // On the first level we can omit the shufflevector <0, undef,...>. So the
    69 lib/Analysis/CostModel.cpp:    // input to the other shufflevector <1, undef> must match with one of the
    70 lib/Analysis/CostModel.cpp:    //  %NextLevelOpL = shufflevector %R, <1, undef ...>
    71 lib/Analysis/CostModel.cpp:  // Shuffle mask for pairwise operation must match.
    72 lib/Analysis/CostModel.cpp:  if (matchPairwiseShuffleMask(LS, true, Level)) {
    73 lib/Analysis/CostModel.cpp:    if (!matchPairwiseShuffleMask(RS, false, Level))
    74 lib/Analysis/CostModel.cpp:  } else if (matchPairwiseShuffleMask(RS, true, Level)) {
    75 lib/Analysis/CostModel.cpp:    if (!matchPairwiseShuffleMask(LS, false, Level))
    76 lib/Analysis/CostModel.cpp:  // We look for a sequence of shuffle,shuffle,add triples like the following
    77 lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
    78 lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
    79 lib/Analysis/CostModel.cpp:  // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
    80 lib/Analysis/CostModel.cpp:  // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
    81 lib/Analysis/CostModel.cpp:static std::pair<Value *, ShuffleVectorInst *>
    82 lib/Analysis/CostModel.cpp:getShuffleAndOtherOprd(BinaryOperator *B) {
    83 lib/Analysis/CostModel.cpp:  ShuffleVectorInst *S = 0;
    84 lib/Analysis/CostModel.cpp:  if ((S = dyn_cast<ShuffleVectorInst>(L)))
    85 lib/Analysis/CostModel.cpp:  S = dyn_cast<ShuffleVectorInst>(R);
    86 lib/Analysis/CostModel.cpp:  // We look for a sequence of shuffles and adds like the following matching one
    87 lib/Analysis/CostModel.cpp:  // fadd, shuffle vector pair at a time.
    88 lib/Analysis/CostModel.cpp:  // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
    89 lib/Analysis/CostModel.cpp:  // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
    90 lib/Analysis/CostModel.cpp:  SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
    91 lib/Analysis/CostModel.cpp:    ShuffleVectorInst *Shuffle;
    92 lib/Analysis/CostModel.cpp:    std::tie(NextRdxOp, Shuffle) = getShuffleAndOtherOprd(BinOp);
    93 lib/Analysis/CostModel.cpp:    // Check the current reduction operation and the shuffle use the same value.
    94 lib/Analysis/CostModel.cpp:    if (Shuffle == 0)
    95 lib/Analysis/CostModel.cpp:    if (Shuffle->getOperand(0) != NextRdxOp)
    96 lib/Analysis/CostModel.cpp:    // Check that shuffle masks matches.
    97 lib/Analysis/CostModel.cpp:      ShuffleMask[j] = MaskStart + j;
    98 lib/Analysis/CostModel.cpp:    std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
    99 lib/Analysis/CostModel.cpp:    SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
    100 lib/Analysis/CostModel.cpp:    if (!matchMask(ShuffleMask, Mask))
    101 lib/Analysis/CostModel.cpp:    // Try to match a reduction sequence (series of shufflevector and vector
    102 lib/Analysis/CostModel.cpp:  case Instruction::ShuffleVector: {
    103 lib/Analysis/CostModel.cpp:    const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
    104 lib/Analysis/CostModel.cpp:    Type *VecTypOp0 = Shuffle->getOperand(0)->getType();
    105 lib/Analysis/CostModel.cpp:    SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
    106 lib/Analysis/CostModel.cpp:      return TTI->getShuffleCost(TargetTransformInfo::SK_Reverse, VecTypOp0, 0,
    107 lib/Analysis/Lint.cpp:  // TODO: Look through vector insert/extract/shuffle.
    108 lib/Analysis/TargetTransformInfo.cpp:unsigned TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Tp,
    109 lib/Analysis/TargetTransformInfo.cpp:  return PrevTTI->getShuffleCost(Kind, Tp, Index, SubTp);
    110 lib/Analysis/TargetTransformInfo.cpp:  unsigned getShuffleCost(ShuffleKind Kind, Type *Ty,
    111 lib/AsmParser/LLLexer.cpp:  INSTKEYWORD(shufflevector,  ShuffleVector);
    112 lib/AsmParser/LLParser.cpp:  case lltok::kw_shufflevector:
    113 lib/AsmParser/LLParser.cpp:    } else if (Opc == Instruction::ShuffleVector) {
    114 lib/AsmParser/LLParser.cpp:        return Error(ID.Loc, "expected three operands to shufflevector");
    115 lib/AsmParser/LLParser.cpp:      if (!ShuffleVectorInst::isValidOperands(Elts[0], Elts[1], Elts[2]))
    116 lib/AsmParser/LLParser.cpp:        return Error(ID.Loc, "invalid operands to shufflevector");
    117 lib/AsmParser/LLParser.cpp:                 ConstantExpr::getShuffleVector(Elts[0], Elts[1],Elts[2]);
    118 lib/AsmParser/LLParser.cpp:  case lltok::kw_shufflevector:  return ParseShuffleVector(Inst, PFS);
    119 lib/AsmParser/LLParser.cpp:/// ParseShuffleVector
    120 lib/AsmParser/LLParser.cpp:///   ::= 'shufflevector' TypeAndValue ',' TypeAndValue ',' TypeAndValue
    121 lib/AsmParser/LLParser.cpp:bool LLParser::ParseShuffleVector(Instruction *&Inst, PerFunctionState &PFS) {
    122 lib/AsmParser/LLParser.cpp:      ParseToken(lltok::comma, "expected ',' after shuffle mask") ||
    123 lib/AsmParser/LLParser.cpp:      ParseToken(lltok::comma, "expected ',' after shuffle value") ||
    124 lib/AsmParser/LLParser.cpp:  if (!ShuffleVectorInst::isValidOperands(Op0, Op1, Op2))
    125 lib/AsmParser/LLParser.cpp:    return Error(Loc, "invalid shufflevector operands");
    126 lib/AsmParser/LLParser.cpp:  Inst = new ShuffleVectorInst(Op0, Op1, Op2);
    127 lib/AsmParser/LLParser.h:    bool ParseShuffleVector(Instruction *&I, PerFunctionState &PFS);
    128 lib/AsmParser/LLToken.h:    kw_extractelement, kw_insertelement, kw_shufflevector,
    129 lib/CodeGen/BasicTargetTransformInfo.cpp:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
    130 lib/CodeGen/BasicTargetTransformInfo.cpp:unsigned BasicTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
    131 lib/CodeGen/BasicTargetTransformInfo.cpp:  // Assume the pairwise shuffles add a cost.
    132 lib/CodeGen/BasicTargetTransformInfo.cpp:  unsigned ShuffleCost =
    133 lib/CodeGen/BasicTargetTransformInfo.cpp:      TopTTI->getShuffleCost(SK_ExtractSubvector, Ty, NumVecElts / 2, Ty);
    134 lib/CodeGen/BasicTargetTransformInfo.cpp:  return ShuffleCost + ArithCost + getScalarizationOverhead(Ty, false, true);
    135 lib/CodeGen/CodeGenPrepare.cpp:    bool OptimizeShuffleVectorInst(ShuffleVectorInst *SI);
    136 lib/CodeGen/CodeGenPrepare.cpp:static bool isBroadcastShuffle(ShuffleVectorInst *SVI) {
    137 lib/CodeGen/CodeGenPrepare.cpp:  SmallVector<int, 16> Mask(SVI->getShuffleMask());
    138 lib/CodeGen/CodeGenPrepare.cpp:/// it's often worth sinking a shufflevector splat down to its use so that
    139 lib/CodeGen/CodeGenPrepare.cpp:bool CodeGenPrepare::OptimizeShuffleVectorInst(ShuffleVectorInst *SVI) {
    140 lib/CodeGen/CodeGenPrepare.cpp:  // We only expect better codegen by sinking a shuffle if we can recognise a
    141 lib/CodeGen/CodeGenPrepare.cpp:  if (!isBroadcastShuffle(SVI))
    142 lib/CodeGen/CodeGenPrepare.cpp:  // InsertedShuffles - Only insert a shuffle in each block once.
    143 lib/CodeGen/CodeGenPrepare.cpp:  DenseMap<BasicBlock*, Instruction*> InsertedShuffles;
    144 lib/CodeGen/CodeGenPrepare.cpp:    // Everything checks out, sink the shuffle if the user's block doesn't
    145 lib/CodeGen/CodeGenPrepare.cpp:    Instruction *&InsertedShuffle = InsertedShuffles[UserBB];
    146 lib/CodeGen/CodeGenPrepare.cpp:    if (!InsertedShuffle) {
    147 lib/CodeGen/CodeGenPrepare.cpp:      InsertedShuffle = new ShuffleVectorInst(SVI->getOperand(0),
    148 lib/CodeGen/CodeGenPrepare.cpp:    User->replaceUsesOfWith(SVI, InsertedShuffle);
    149 lib/CodeGen/CodeGenPrepare.cpp:  // If we removed all uses, nuke the shuffle.
    150 lib/CodeGen/CodeGenPrepare.cpp:  if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(I))
    151 lib/CodeGen/CodeGenPrepare.cpp:    return OptimizeShuffleVectorInst(SVI);
    152 lib/CodeGen/MachineScheduler.cpp:// Machine Instruction Shuffler for Correctness Testing
    153 lib/CodeGen/MachineScheduler.cpp:class InstructionShuffler : public MachineSchedStrategy {
    154 lib/CodeGen/MachineScheduler.cpp:  InstructionShuffler(bool alternate, bool topdown)
    155 lib/CodeGen/MachineScheduler.cpp:static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
    156 lib/CodeGen/MachineScheduler.cpp:  return new ScheduleDAGMILive(C, new InstructionShuffler(Alternate, TopDown));
    157 lib/CodeGen/MachineScheduler.cpp:static MachineSchedRegistry ShufflerRegistry(
    158 lib/CodeGen/MachineScheduler.cpp:  "shuffle", "Shuffle machine instructions alternating directions",
    159 lib/CodeGen/MachineScheduler.cpp:  createInstructionShuffler);
    160 lib/CodeGen/TargetLoweringBase.cpp:  case ShuffleVector:  return ISD::VECTOR_SHUFFLE;
    161 lib/IR/AsmWriter.cpp:    // Select, Store and ShuffleVector always print all types.
    162 lib/IR/AsmWriter.cpp:    if (isa<SelectInst>(I) || isa<StoreInst>(I) || isa<ShuffleVectorInst>(I)
    163 lib/IR/AutoUpgrade.cpp:        Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
    164 lib/IR/ConstantFold.cpp:Constant *llvm::ConstantFoldShuffleVectorInstruction(Constant *V1,
    165 lib/IR/ConstantFold.cpp:  // Undefined shuffle mask -> undefined value.
    166 lib/IR/ConstantFold.cpp:  // Loop over the shuffle mask, evaluating each element.
    167 lib/IR/ConstantFold.cpp:    int Elt = ShuffleVectorInst::getMaskValue(Mask, i);
    168 lib/IR/ConstantFold.h:  Constant *ConstantFoldShuffleVectorInstruction(Constant *V1, Constant *V2,
    169 lib/IR/Constants.cpp:  case Instruction::ShuffleVector:
    170 lib/IR/Constants.cpp:    return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]);
    171 lib/IR/Constants.cpp:Constant *ConstantExpr::getShuffleVector(Constant *V1, Constant *V2,
    172 lib/IR/Constants.cpp:  assert(ShuffleVectorInst::isValidOperands(V1, V2, Mask) &&
    173 lib/IR/Constants.cpp:         "Invalid shuffle vector constant expr operands!");
    174 lib/IR/Constants.cpp:  if (Constant *FC = ConstantFoldShuffleVectorInstruction(V1, V2, Mask))
    175 lib/IR/Constants.cpp:  const ExprMapKeyType Key(Instruction::ShuffleVector, ArgVec);
    176 lib/IR/Constants.cpp:  case Instruction::ShuffleVector:
    177 lib/IR/Constants.cpp:    return new ShuffleVectorInst(Ops[0], Ops[1], Ops[2]);
    178 lib/IR/ConstantsContext.h:/// ShuffleVectorConstantExpr - This class is private to
    179 lib/IR/ConstantsContext.h:/// shufflevector constant exprs.
    180 lib/IR/ConstantsContext.h:class ShuffleVectorConstantExpr : public ConstantExpr {
    181 lib/IR/ConstantsContext.h:  ShuffleVectorConstantExpr(Constant *C1, Constant *C2, Constant *C3)
    182 lib/IR/ConstantsContext.h:                 Instruction::ShuffleVector,
    183 lib/IR/ConstantsContext.h:struct OperandTraits<ShuffleVectorConstantExpr> :
    184 lib/IR/ConstantsContext.h:    public FixedNumOperandTraits<ShuffleVectorConstantExpr, 3> {
    185 lib/IR/ConstantsContext.h:DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorConstantExpr, Value)
    186 lib/IR/ConstantsContext.h:    if (V.opcode == Instruction::ShuffleVector)
    187 lib/IR/ConstantsContext.h:      return new ShuffleVectorConstantExpr(V.operands[0], V.operands[1],
    188 lib/IR/Core.cpp:LLVMValueRef LLVMConstShuffleVector(LLVMValueRef VectorAConstant,
    189 lib/IR/Core.cpp:  return wrap(ConstantExpr::getShuffleVector(unwrap<Constant>(VectorAConstant),
    190 lib/IR/Core.cpp:LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef B, LLVMValueRef V1,
    191 lib/IR/Core.cpp:  return wrap(unwrap(B)->CreateShuffleVector(unwrap(V1), unwrap(V2),
    192 lib/IR/Instruction.cpp:  case ShuffleVector:  return "shufflevector";
    193 lib/IR/Instructions.cpp://                      ShuffleVectorInst Implementation
    194 lib/IR/Instructions.cpp:ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
    195 lib/IR/Instructions.cpp:              ShuffleVector,
    196 lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::op_begin(this),
    197 lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::operands(this),
    198 lib/IR/Instructions.cpp:         "Invalid shuffle vector instruction operands!");
    199 lib/IR/Instructions.cpp:ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
    200 lib/IR/Instructions.cpp:              ShuffleVector,
    201 lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::op_begin(this),
    202 lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::operands(this),
    203 lib/IR/Instructions.cpp:         "Invalid shuffle vector instruction operands!");
    204 lib/IR/Instructions.cpp:bool ShuffleVectorInst::isValidOperands(const Value *V1, const Value *V2,
    205 lib/IR/Instructions.cpp:  // used as the shuffle mask. When this occurs, the shuffle mask will
    206 lib/IR/Instructions.cpp:/// getMaskValue - Return the index from the shuffle mask for the specified
    207 lib/IR/Instructions.cpp:int ShuffleVectorInst::getMaskValue(Constant *Mask, unsigned i) {
    208 lib/IR/Instructions.cpp:/// getShuffleMask - Return the full mask for this instruction, where each
    209 lib/IR/Instructions.cpp:void ShuffleVectorInst::getShuffleMask(Constant *Mask,
    210 lib/IR/Instructions.cpp:ShuffleVectorInst *ShuffleVectorInst::clone_impl() const {
    211 lib/IR/Instructions.cpp:  return new ShuffleVectorInst(getOperand(0), getOperand(1), getOperand(2));
    212 lib/IR/LLVMContextImpl.cpp:void ShuffleVectorConstantExpr::anchor() { }
    213 lib/IR/Verifier.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &EI);
    214 lib/IR/Verifier.cpp:void Verifier::visitShuffleVectorInst(ShuffleVectorInst &SV) {
    215 lib/IR/Verifier.cpp:  Assert1(ShuffleVectorInst::isValidOperands(SV.getOperand(0), SV.getOperand(1),
    216 lib/IR/Verifier.cpp:          "Invalid shufflevector operands!", &SV);
    217 Robs-MacBook-Pro:llvm cameron$
    218 Robs-MacBook-Pro:llvm cameron$ fgrep huffle [li]*/*/*/*.*
    219 include/llvm/ADT/IntervalMap.h:    assert(CurSize[n] == NewSize[n] && "Insufficient element shuffle");
    220 include/llvm/Analysis/TargetFolder.h:  Constant *CreateShuffleVector(Constant *V1, Constant *V2,
    221 include/llvm/Analysis/TargetFolder.h:    return Fold(ConstantExpr::getShuffleVector(V1, V2, Mask));
    222 include/llvm/Analysis/TargetTransformInfo.h:  /// \brief The various kinds of shuffle patterns for vector queries.
    223 include/llvm/Analysis/TargetTransformInfo.h:  enum ShuffleKind {
    224 include/llvm/Analysis/TargetTransformInfo.h:  /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
    225 include/llvm/Analysis/TargetTransformInfo.h:  /// extraction shuffle kinds.
    226 include/llvm/Analysis/TargetTransformInfo.h:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, int Index = 0,
    227 include/llvm/CodeGen/ISDOpcodes.h:    /// ShuffleVectorSDNode class.  This is quite similar to the Altivec
    228 include/llvm/CodeGen/SelectionDAG.h:  /// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node.  The number of
    229 include/llvm/CodeGen/SelectionDAG.h:  SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
    230 include/llvm/CodeGen/SelectionDAGNodes.h:/// ShuffleVectorSDNode - This SDNode is used to implement the code generator
    231 include/llvm/CodeGen/SelectionDAGNodes.h:/// support for the llvm IR shufflevector instruction.  It combines elements
    232 include/llvm/CodeGen/SelectionDAGNodes.h:/// the shuffle mask.  For input vectors of width N, mask indices of 0..N-1
    233 include/llvm/CodeGen/SelectionDAGNodes.h:class ShuffleVectorSDNode : public SDNode {
    234 include/llvm/CodeGen/SelectionDAGNodes.h:  ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1,
    235 include/llvm/IR/ConstantFolder.h:  Constant *CreateShuffleVector(Constant *V1, Constant *V2,
    236 include/llvm/IR/ConstantFolder.h:    return ConstantExpr::getShuffleVector(V1, V2, Mask);
    237 include/llvm/IR/Constants.h:  static Constant *getShuffleVector(Constant *V1, Constant *V2, Constant *Mask);
    238 include/llvm/IR/IRBuilder.h:  Value *CreateShuffleVector(Value *V1, Value *V2, Value *Mask,
    239 include/llvm/IR/IRBuilder.h:          return Insert(Folder.CreateShuffleVector(V1C, V2C, MC), Name);
    240 include/llvm/IR/IRBuilder.h:    return Insert(new ShuffleVectorInst(V1, V2, Mask), Name);
    241 include/llvm/IR/IRBuilder.h:    // First insert it into an undef vector so we can shuffle it.
    242 include/llvm/IR/IRBuilder.h:    // Shuffle the value across the desired number of elements.
    243 include/llvm/IR/IRBuilder.h:    return CreateShuffleVector(V, Undef, Zeros, Name + ".splat");
    244 include/llvm/IR/InstVisitor.h:  RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction);}
    245 include/llvm/IR/Instruction.def:HANDLE_OTHER_INST(56, ShuffleVector, ShuffleVectorInst)  // shuffle two vectors.
    246 include/llvm/IR/Instructions.h://                           ShuffleVectorInst Class
    247 include/llvm/IR/Instructions.h:/// ShuffleVectorInst - This instruction constructs a fixed permutation of two
    248 include/llvm/IR/Instructions.h:class ShuffleVectorInst : public Instruction {
    249 include/llvm/IR/Instructions.h:  ShuffleVectorInst *clone_impl() const override;
    250 include/llvm/IR/Instructions.h:  ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
    251 include/llvm/IR/Instructions.h:  ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
    252 include/llvm/IR/Instructions.h:  /// isValidOperands - Return true if a shufflevector instruction can be
    253 include/llvm/IR/Instructions.h:  /// getMaskValue - Return the index from the shuffle mask for the specified
    254 include/llvm/IR/Instructions.h:  /// getShuffleMask - Return the full mask for this instruction, where each
    255 include/llvm/IR/Instructions.h:  static void getShuffleMask(Constant *Mask, SmallVectorImpl<int> &Result);
    256 include/llvm/IR/Instructions.h:  void getShuffleMask(SmallVectorImpl<int> &Result) const {
    257 include/llvm/IR/Instructions.h:    return getShuffleMask(getMask(), Result);
    258 include/llvm/IR/Instructions.h:  SmallVector<int, 16> getShuffleMask() const {
    259 include/llvm/IR/Instructions.h:    getShuffleMask(Mask);
    260 include/llvm/IR/Instructions.h:    return I->getOpcode() == Instruction::ShuffleVector;
    261 include/llvm/IR/Instructions.h:struct OperandTraits<ShuffleVectorInst> :
    262 include/llvm/IR/Instructions.h:  public FixedNumOperandTraits<ShuffleVectorInst, 3> {
    263 include/llvm/IR/Instructions.h:DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorInst, Value)
    264 include/llvm/IR/IntrinsicsPowerPC.td:  // vpkuhum is lowered to a shuffle.
    265 include/llvm/IR/IntrinsicsPowerPC.td:  // vpkuwum is lowered to a shuffle.
    266 include/llvm/IR/IntrinsicsX86.td:// Shuffle ops
    267 include/llvm/IR/NoFolder.h:  Instruction *CreateShuffleVector(Constant *V1, Constant *V2,
    268 include/llvm/IR/NoFolder.h:    return new ShuffleVectorInst(V1, V2, Mask);
    269 include/llvm/Target/TargetLowering.h:  virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
    270 include/llvm/Target/TargetLowering.h:  /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
    271 include/llvm/Target/TargetSelectionDAG.td:def SDTVecShuffle : SDTypeProfile<1, 2, [
    272 include/llvm/Target/TargetSelectionDAG.td:def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
    273 lib/Bitcode/Reader/BitcodeReader.cpp:      V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
    274 lib/Bitcode/Reader/BitcodeReader.cpp:      V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
    275 lib/Bitcode/Reader/BitcodeReader.cpp:      I = new ShuffleVectorInst(Vec1, Vec2, Mask);
    276 lib/Bitcode/Writer/BitcodeWriter.cpp:      case Instruction::ShuffleVector:
    277 lib/Bitcode/Writer/BitcodeWriter.cpp:        // standard shufflevector instruction.  If the types are different,
    278 lib/Bitcode/Writer/BitcodeWriter.cpp:        // then the shuffle is widening or truncating the input vectors, and
    279 lib/Bitcode/Writer/BitcodeWriter.cpp:  case Instruction::ShuffleVector:
    280 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    SDValue XformToShuffleWithZero(SDNode *N);
    281 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
    282 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // If both shuffles use the same mask, and both shuffle within a single
    283 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // vector types from memory. In many cases this allows additional shuffle
    284 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
    285 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
    286 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:           "Inputs to shuffles are not the same type");
    287 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // Check that both shuffles use the same mask. The masks are known to be of
    288 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      return DAG.getVectorShuffle(VT, SDLoc(N), Op,
    289 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
    290 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Perform only after legalization to ensure build_vector / vector_shuffle
    291 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
    292 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    const ShuffleVectorSDNode *SVN = NULL;
    293 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
    294 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
    295 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // using shuffles.
    296 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // turn into a single shuffle instruction.
    297 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // at most two distinct vectors, turn this into a shuffle node.
    298 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // May only combine to shuffle after legalize if shuffle is legal.
    299 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // If everything is good, we can make a shuffle operation.
    300 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // We can't generate a shuffle node with mismatched input and output types.
    301 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
    302 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
    303 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // inputs come from at most two distinct vectors, turn this into a shuffle
    304 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:// Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
    305 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
    306 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
    307 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
    308 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Canonicalize shuffle undef, undef -> undef
    309 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
    310 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Canonicalize shuffle v, v -> v, undef
    311 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
    312 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Canonicalize shuffle undef, v -> v, undef.  Commute the shuffle mask.
    313 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
    314 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
    315 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    SDValue V = partitionShuffleOfConcats(N, DAG);
    316 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // If this shuffle node is simply a swizzle of another shuffle node,
    317 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // and it reverses the swizzle of the previous shuffle then we can
    318 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // optimize shuffle(shuffle(x, undef), undef) -> x.
    319 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
    320 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // Shuffle nodes can only reverse shuffles with a single non-undef value.
    321 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // The incoming shuffle must be of the same type as the result of the
    322 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // current shuffle.
    323 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:           "Shuffle types don't match");
    324 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // shuffle. Adopt the incoming index.
    325 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // The combined shuffle must map each index to itself.
    326 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
    327 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:/// an AND to a vector_shuffle with the destination vector and a zero vector.
    328 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:///      vector_shuffle V, Zero, <0, 4, 2, 4>
    329 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
    330 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // Let's see if the target supports this vector_shuffle.
    331 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
    332 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  SDValue Shuffle = XformToShuffleWithZero(N);
    333 lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  if (Shuffle.getNode()) return Shuffle;
    334 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
    335 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  /// whose vector element type is narrower than the original shuffle type.
    336 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
    337 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
    338 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:/// whose vector element type is narrower than the original shuffle type.
    339 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT,  SDLoc dl,
    340 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
    341 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
    342 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
    343 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      // We generate a shuffle of InVec and ScVec, so the shuffle mask
    344 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
    345 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    SmallVector<int, 8> ShuffleVec(NumElems, -1);
    346 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      ShuffleVec[i] = V == Value1 ? 0 : NumElems;
    347 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
    348 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      // Return shuffle(LowValVec, undef, <0,0,0,0>)
    349 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
    350 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
    351 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:        // Convert shuffle node.
    352 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:        // Convert the shuffle mask
    353 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
    354 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    // Convert the shuffle mask to the right # elements.
    355 lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
    356 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
    357 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:  return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
    358 lib/CodeGen/SelectionDAG/LegalizeTypes.h:  void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
    359 lib/CodeGen/SelectionDAG/LegalizeTypes.h:  SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
    360 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
    361 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
    362 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:  // express it as a vector shuffle of those two inputs.  Otherwise extract the
    363 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    // Build a shuffle mask for the output, discovering on the fly which
    364 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    // input vectors to use as shuffle operands (recorded in InputUsed).
    365 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    // If building a suitable shuffle vector proves too hard, then bail
    366 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      // Find or create a shuffle vector operand to hold this input.
    367 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:        // shuffle vector.  Insert all elements into a BUILD_VECTOR instead.
    368 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      // Add the mask index for the new shuffle vector.
    369 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      // At least one input vector was used.  Create a new shuffle vector.
    370 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      Output =  DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
    371 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
    372 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:        // Replace concat of two operands with a shuffle.
    373 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:        return DAG.getVectorShuffle(WidenVT, dl,
    374 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
    375 lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:  return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
    376 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
    377 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  assert(!isa<ShuffleVectorSDNode>(N) && "Bad ShuffleVectorSDNode!");
    378 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    // vector shuffle in this situation). However, we do not need any code to
    379 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
    380 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:// the shuffle mask M that point at N1 to point at N2, and indices that point
    381 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
    382 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:SDValue SelectionDAG::getVectorShuffle(EVT VT, SDLoc dl, SDValue N1,
    383 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize shuffle undef, undef -> undef
    384 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // input to the shuffle.
    385 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize shuffle v, v -> v, undef
    386 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize shuffle undef, v -> v, undef.  Commute the shuffle mask.
    387 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    commuteShuffle(N1, N2, MaskVec);
    388 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize all index into lhs, -> shuffle lhs, undef
    389 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize all index into rhs, -> shuffle rhs, undef
    390 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    commuteShuffle(N1, N2, MaskVec);
    391 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // If Identity shuffle return that node.
    392 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  ShuffleVectorSDNode *N =
    393 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    new (NodeAllocator) ShuffleVectorSDNode(VT, dl.getIROrder(),
    394 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    llvm_unreachable("should use getVectorShuffle constructor!");
    395 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) {
    396 lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Find the first non-undef value in the shuffle mask.
    397 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:      // Vector widening case, e.g. <2 x float> -> <4 x float>.  Shuffle in
    398 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:// Utility for visitShuffleVector - Return true if every element in Mask,
    399 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:void SelectionDAGBuilder::visitShuffleVector(const User &I) {
    400 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:  ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
    401 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:    setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
    402 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:  // Normalize the shuffle vector since mask and vector length don't match.
    403 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:        // The shuffle is concatenating two vectors together.
    404 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:        // The shuffle is concatenating two vectors together.
    405 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:    setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
    406 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:    // two subvectors and do the shuffle. The analysis is done by calculating
    407 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:      // Extract appropriate subvector and generate a vector shuffle
    408 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:      setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
    409 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:  // replacing the shuffle with extract and build vector.
    410 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h:class ShuffleVectorInst;
    411 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h:  void visitShuffleVector(const User &I);
    412 lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp:  case ISD::VECTOR_SHUFFLE:             return "vector_shuffle";
    413 lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp:  } else if (const ShuffleVectorSDNode *SVN =
    414 lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp:               dyn_cast<ShuffleVectorSDNode>(this)) {
    415 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
    416 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:  case Instruction::ShuffleVector:  NumFastIselFailShuffleVector++; return;
    417 lib/ExecutionEngine/Interpreter/Execution.cpp:void Interpreter::visitShuffleVectorInst(ShuffleVectorInst &I){
    418 lib/ExecutionEngine/Interpreter/Execution.cpp:    llvm_unreachable("Unhandled dest type for shufflevector instruction");
    419 lib/ExecutionEngine/Interpreter/Execution.cpp:  // shufflevector instruction.
    420 lib/ExecutionEngine/Interpreter/Execution.cpp:          // %tmp = shufflevector <2 x i32> <i32 3, i32 4>, <2 x i32> undef,
    421 lib/ExecutionEngine/Interpreter/Execution.cpp:          llvm_unreachable("Invalid mask in shufflevector instruction");
    422 lib/ExecutionEngine/Interpreter/Execution.cpp:          llvm_unreachable("Invalid mask in shufflevector instruction");
    423 lib/ExecutionEngine/Interpreter/Execution.cpp:          llvm_unreachable("Invalid mask in shufflevector instruction");
    424 lib/ExecutionEngine/Interpreter/Interpreter.h:  void visitShuffleVectorInst(ShuffleVectorInst &I);
    425 lib/Target/AArch64/AArch64ISelLowering.cpp:  SDValue ShuffleVec
    426 lib/Target/AArch64/AArch64ISelLowering.cpp:    = DAG.getVectorShuffle(DestVT, SDLoc(N), Sext, DAG.getUNDEF(DestVT), Mask);
    427 lib/Target/AArch64/AArch64ISelLowering.cpp:                SubRegVT, ShuffleVec,
    428 lib/Target/AArch64/AArch64ISelLowering.cpp:// Check whether a shuffle_vector could be presented as concat_vector.
    429 lib/Target/AArch64/AArch64ISelLowering.cpp:// Check whether a Build Vector could be presented as Shuffle Vector.
    430 lib/Target/AArch64/AArch64ISelLowering.cpp:// This Shuffle Vector maybe not legalized, so the length of its operand and
    431 lib/Target/AArch64/AArch64ISelLowering.cpp:bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
    432 lib/Target/AArch64/AArch64ISelLowering.cpp:  // Try to lower this in lowering ShuffleVector way.
    433 lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isKnownShuffleVector(Op, DAG, V0, V1, Mask)) {
    434 lib/Target/AArch64/AArch64ISelLowering.cpp:      SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
    435 lib/Target/AArch64/AArch64ISelLowering.cpp:      if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
    436 lib/Target/AArch64/AArch64ISelLowering.cpp:        return Shuffle;
    437 lib/Target/AArch64/AArch64ISelLowering.cpp:        return LowerVECTOR_SHUFFLE(Shuffle, DAG);
    438 lib/Target/AArch64/AArch64ISelLowering.cpp:  // scalar_to_vector for the elements followed by a shuffle (provided the
    439 lib/Target/AArch64/AArch64ISelLowering.cpp:  // shuffle is valid for the target) and materialization element by element
    440 lib/Target/AArch64/AArch64ISelLowering.cpp:/// isREVMask - Check if a vector shuffle corresponds to a REV
    441 lib/Target/AArch64/AArch64ISelLowering.cpp:  // If the first shuffle index is UNDEF, be optimistic.
    442 lib/Target/AArch64/AArch64ISelLowering.cpp:// isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and
    443 lib/Target/AArch64/AArch64ISelLowering.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
    444 lib/Target/AArch64/AArch64ISelLowering.cpp:  // Convert shuffles that are directly supported on NEON to target-specific
    445 lib/Target/AArch64/AArch64ISelLowering.cpp:  // DAG nodes, instead of keeping them as shuffles and matching them again
    446 lib/Target/AArch64/AArch64ISelLowering.cpp:  ArrayRef<int> ShuffleMask = SVN->getMask();
    447 lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isREVMask(ShuffleMask, VT, 64))
    448 lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isREVMask(ShuffleMask, VT, 32))
    449 lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isREVMask(ShuffleMask, VT, 16))
    450 lib/Target/AArch64/AArch64ISelLowering.cpp:    ISDNo = isPermuteMask(ShuffleMask, VT, true);
    451 lib/Target/AArch64/AArch64ISelLowering.cpp:    ISDNo = isPermuteMask(ShuffleMask, VT, false);
    452 lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isConcatVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
    453 lib/Target/AArch64/AArch64ISelLowering.cpp:  // If the element of shuffle mask are all the same constant, we can
    454 lib/Target/AArch64/AArch64ISelLowering.cpp:  if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
    455 lib/Target/AArch64/AArch64ISelLowering.cpp:  int Length = ShuffleMask.size();
    456 lib/Target/AArch64/AArch64ISelLowering.cpp:  // If the number of v1 elements is the same as the number of shuffle mask
    457 lib/Target/AArch64/AArch64ISelLowering.cpp:  // element and the shuffle masks are sequential values, we can transform
    458 lib/Target/AArch64/AArch64ISelLowering.cpp:    // Check if the shuffle mask is sequential.
    459 lib/Target/AArch64/AArch64ISelLowering.cpp:    while (ShuffleMask[SkipUndef] == -1) {
    460 lib/Target/AArch64/AArch64ISelLowering.cpp:    int CurMask = ShuffleMask[SkipUndef];
    461 lib/Target/AArch64/AArch64ISelLowering.cpp:        if (ShuffleMask[I] != -1 && ShuffleMask[I] != CurMask) {
    462 lib/Target/AArch64/AArch64ISelLowering.cpp:        unsigned Index = (EltSize / 8) * (ShuffleMask[SkipUndef] - SkipUndef);
    463 lib/Target/AArch64/AArch64ISelLowering.cpp:  // For shuffle mask like "0, 1, 2, 3, 4, 5, 13, 7", try to generate insert
    464 lib/Target/AArch64/AArch64ISelLowering.cpp:  // If shuffle mask is like "0, 1, 10, 11, 12, 13, 14, 15", V2 would be a
    465 lib/Target/AArch64/AArch64ISelLowering.cpp:    if (ShuffleMask[I] != I) {
    466 lib/Target/AArch64/AArch64ISelLowering.cpp:      NV1Elt.push_back(ShuffleMask[I]);
    467 lib/Target/AArch64/AArch64ISelLowering.cpp:    if (ShuffleMask[I] != (I + V1EltNum)) {
    468 lib/Target/AArch64/AArch64ISelLowering.cpp:      NV2Elt.push_back(ShuffleMask[I]);
    469 lib/Target/AArch64/AArch64ISelLowering.h:  bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &V0,
    470 lib/Target/ARM/ARMISelLowering.cpp:#include "ARMPerfectShuffle.h"
    471 lib/Target/ARM/ARMISelLowering.cpp:// check if an VEXT instruction can handle the shuffle mask when the
    472 lib/Target/ARM/ARMISelLowering.cpp:// vector sources of the shuffle are the same.
    473 lib/Target/ARM/ARMISelLowering.cpp:  // Assume that the first shuffle index is not UNDEF.  Fail if it is.
    474 lib/Target/ARM/ARMISelLowering.cpp:  // If this is a VEXT shuffle, the immediate value is the index of the first
    475 lib/Target/ARM/ARMISelLowering.cpp:  // element.  The other shuffle indices must be the successive elements after
    476 lib/Target/ARM/ARMISelLowering.cpp:  // Assume that the first shuffle index is not UNDEF.  Fail if it is.
    477 lib/Target/ARM/ARMISelLowering.cpp:  // If this is a VEXT shuffle, the immediate value is the index of the first
    478 lib/Target/ARM/ARMISelLowering.cpp:  // element.  The other shuffle indices must be the successive elements after
    479 lib/Target/ARM/ARMISelLowering.cpp:/// isVREVMask - Check if a vector shuffle corresponds to a VREV
    480 lib/Target/ARM/ARMISelLowering.cpp:  // If the first shuffle index is UNDEF, be optimistic.
    481 lib/Target/ARM/ARMISelLowering.cpp:  // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
    482 lib/Target/ARM/ARMISelLowering.cpp:/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
    483 lib/Target/ARM/ARMISelLowering.cpp:/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
    484 lib/Target/ARM/ARMISelLowering.cpp:/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
    485 lib/Target/ARM/ARMISelLowering.cpp:    SDValue shuffle = ReconstructShuffle(Op, DAG);
    486 lib/Target/ARM/ARMISelLowering.cpp:    if (shuffle != SDValue())
    487 lib/Target/ARM/ARMISelLowering.cpp:      return shuffle;
    488 lib/Target/ARM/ARMISelLowering.cpp:  // scalar_to_vector for the elements followed by a shuffle (provided the
    489 lib/Target/ARM/ARMISelLowering.cpp:  // shuffle is valid for the target) and materialization element by element
    490 lib/Target/ARM/ARMISelLowering.cpp:// shuffle in combination with VEXTs.
    491 lib/Target/ARM/ARMISelLowering.cpp:SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
    492 lib/Target/ARM/ARMISelLowering.cpp:      // A shuffle can only come from building a vector from various
    493 lib/Target/ARM/ARMISelLowering.cpp:      // This code doesn't know how to handle shuffles where the vector
    494 lib/Target/ARM/ARMISelLowering.cpp:  SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
    495 lib/Target/ARM/ARMISelLowering.cpp:  // and prepares appropriate SDValues for a shuffle if possible.
    496 lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = SourceVecs[i];
    497 lib/Target/ARM/ARMISelLowering.cpp:      // break it down again in a shuffle.
    498 lib/Target/ARM/ARMISelLowering.cpp:           "unexpected vector sizes in ReconstructShuffle");
    499 lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
    500 lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
    501 lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
    502 lib/Target/ARM/ARMISelLowering.cpp:  if (isShuffleMaskLegal(Mask, VT))
    503 lib/Target/ARM/ARMISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
    504 lib/Target/ARM/ARMISelLowering.cpp:/// isShuffleMaskLegal - Targets can use this to indicate that they only
    505 lib/Target/ARM/ARMISelLowering.cpp:ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
    506 lib/Target/ARM/ARMISelLowering.cpp:    // Compute the index in the perfect shuffle table.
    507 lib/Target/ARM/ARMISelLowering.cpp:    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
    508 lib/Target/ARM/ARMISelLowering.cpp:          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
    509 lib/Target/ARM/ARMISelLowering.cpp:/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
    510 lib/Target/ARM/ARMISelLowering.cpp:/// the specified operations to build the shuffle.
    511 lib/Target/ARM/ARMISelLowering.cpp:static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
    512 lib/Target/ARM/ARMISelLowering.cpp:  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
    513 lib/Target/ARM/ARMISelLowering.cpp:  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
    514 lib/Target/ARM/ARMISelLowering.cpp:  default: llvm_unreachable("Unknown shuffle opcode!");
    515 lib/Target/ARM/ARMISelLowering.cpp:                                       ArrayRef<int> ShuffleMask,
    516 lib/Target/ARM/ARMISelLowering.cpp:         I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
    517 lib/Target/ARM/ARMISelLowering.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
    518 lib/Target/ARM/ARMISelLowering.cpp:  // Convert shuffles that are directly supported on NEON to target-specific
    519 lib/Target/ARM/ARMISelLowering.cpp:  // DAG nodes, instead of keeping them as shuffles and matching them again
    520 lib/Target/ARM/ARMISelLowering.cpp:  ArrayRef<int> ShuffleMask = SVN->getMask();
    521 lib/Target/ARM/ARMISelLowering.cpp:    if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
    522 lib/Target/ARM/ARMISelLowering.cpp:    if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
    523 lib/Target/ARM/ARMISelLowering.cpp:    if (isVREVMask(ShuffleMask, VT, 64))
    524 lib/Target/ARM/ARMISelLowering.cpp:    if (isVREVMask(ShuffleMask, VT, 32))
    525 lib/Target/ARM/ARMISelLowering.cpp:    if (isVREVMask(ShuffleMask, VT, 16))
    526 lib/Target/ARM/ARMISelLowering.cpp:        isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
    527 lib/Target/ARM/ARMISelLowering.cpp:    // Check for Neon shuffles that modify both input vectors in place.
    528 lib/Target/ARM/ARMISelLowering.cpp:    // If both results are used, i.e., if there are two shuffles with the same
    529 lib/Target/ARM/ARMISelLowering.cpp:    // used for both shuffles.
    530 lib/Target/ARM/ARMISelLowering.cpp:    if (isVTRNMask(ShuffleMask, VT, WhichResult))
    531 lib/Target/ARM/ARMISelLowering.cpp:    if (isVUZPMask(ShuffleMask, VT, WhichResult))
    532 lib/Target/ARM/ARMISelLowering.cpp:    if (isVZIPMask(ShuffleMask, VT, WhichResult))
    533 lib/Target/ARM/ARMISelLowering.cpp:    if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
    534 lib/Target/ARM/ARMISelLowering.cpp:    if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
    535 lib/Target/ARM/ARMISelLowering.cpp:    if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
    536 lib/Target/ARM/ARMISelLowering.cpp:  // If the shuffle is not directly supported and it has 4 elements, use
    537 lib/Target/ARM/ARMISelLowering.cpp:  // the PerfectShuffle-generated table to synthesize it from other shuffles.
    538 lib/Target/ARM/ARMISelLowering.cpp:      if (ShuffleMask[i] < 0)
    539 lib/Target/ARM/ARMISelLowering.cpp:        PFIndexes[i] = ShuffleMask[i];
    540 lib/Target/ARM/ARMISelLowering.cpp:    // Compute the index in the perfect shuffle table.
    541 lib/Target/ARM/ARMISelLowering.cpp:    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
    542 lib/Target/ARM/ARMISelLowering.cpp:      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
    543 lib/Target/ARM/ARMISelLowering.cpp:  // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
    544 lib/Target/ARM/ARMISelLowering.cpp:      if (ShuffleMask[i] < 0)
    545 lib/Target/ARM/ARMISelLowering.cpp:                                  ShuffleMask[i] < (int)NumElts ? V1 : V2,
    546 lib/Target/ARM/ARMISelLowering.cpp:                                  DAG.getConstant(ShuffleMask[i] & (NumElts-1),
    547 lib/Target/ARM/ARMISelLowering.cpp:  if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
    548 lib/Target/ARM/ARMISelLowering.cpp:    SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
    549 lib/Target/ARM/ARMISelLowering.cpp:  // Optimize trunc store (of multiple scalars) to shuffle and store.  First,
    550 lib/Target/ARM/ARMISelLowering.cpp:    // Create a type on which we perform the shuffle.
    551 lib/Target/ARM/ARMISelLowering.cpp:    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
    552 lib/Target/ARM/ARMISelLowering.cpp:    for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
    553 lib/Target/ARM/ARMISelLowering.cpp:    // Can't shuffle using an illegal type.
    554 lib/Target/ARM/ARMISelLowering.cpp:    SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
    555 lib/Target/ARM/ARMISelLowering.cpp:                                ShuffleVec.data());
    556 lib/Target/ARM/ARMISelLowering.cpp:  // The LLVM shufflevector instruction does not require the shuffle mask
    557 lib/Target/ARM/ARMISelLowering.cpp:  //   shuffle(concat(v1, undef), concat(v2, undef)) ->
    558 lib/Target/ARM/ARMISelLowering.cpp:  //   shuffle(concat(v1, v2), undef)
    559 lib/Target/ARM/ARMISelLowering.cpp:  // Translate the shuffle mask.
    560 lib/Target/ARM/ARMISelLowering.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
    561 lib/Target/ARM/ARMISelLowering.cpp:  return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
    562 lib/Target/ARM/ARMISelLowering.h:      // Vector shuffles:
    563 lib/Target/ARM/ARMISelLowering.h:      VTBL1,        // 1-register shuffle with mask
    564 lib/Target/ARM/ARMISelLowering.h:      VTBL2,        // 2-register shuffle with mask
    565 lib/Target/ARM/ARMISelLowering.h:      // is fine if BUILD_VECTORs are always lowered to shuffles or other
    566 lib/Target/ARM/ARMISelLowering.h:    bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
    567 lib/Target/ARM/ARMISelLowering.h:    SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
    568 lib/Target/ARM/ARMInstrNEON.td:// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
    569 lib/Target/ARM/ARMInstrNEON.td:class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
    570 lib/Target/ARM/ARMInstrNEON.td:class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
    571 lib/Target/ARM/ARMInstrNEON.td:// Other Vector Shuffles.
    572 lib/Target/ARM/ARMInstrNEON.td:def  VTRNd8   : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
    573 lib/Target/ARM/ARMInstrNEON.td:def  VTRNd16  : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
    574 lib/Target/ARM/ARMInstrNEON.td:def  VTRNd32  : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
    575 lib/Target/ARM/ARMInstrNEON.td:def  VTRNq8   : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
    576 lib/Target/ARM/ARMInstrNEON.td:def  VTRNq16  : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
    577 lib/Target/ARM/ARMInstrNEON.td:def  VTRNq32  : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
    578 lib/Target/ARM/ARMInstrNEON.td:def  VUZPd8   : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
    579 lib/Target/ARM/ARMInstrNEON.td:def  VUZPd16  : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
    580 lib/Target/ARM/ARMInstrNEON.td:def  VUZPq8   : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
    581 lib/Target/ARM/ARMInstrNEON.td:def  VUZPq16  : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
    582 lib/Target/ARM/ARMInstrNEON.td:def  VUZPq32  : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
    583 lib/Target/ARM/ARMInstrNEON.td:def  VZIPd8   : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
    584 lib/Target/ARM/ARMInstrNEON.td:def  VZIPd16  : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
    585 lib/Target/ARM/ARMInstrNEON.td:def  VZIPq8   : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
    586 lib/Target/ARM/ARMInstrNEON.td:def  VZIPq16  : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
    587 lib/Target/ARM/ARMInstrNEON.td:def  VZIPq32  : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
    588 lib/Target/ARM/ARMPerfectShuffle.h://===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table --------*- C++ -*-===//
    589 lib/Target/ARM/ARMPerfectShuffle.h:// This file, which was autogenerated by llvm-PerfectShuffle, contains data
    590 lib/Target/ARM/ARMPerfectShuffle.h:// for the optimal way to build a perfect shuffle using neon instructions.
    591 lib/Target/ARM/ARMPerfectShuffle.h:static const unsigned PerfectShuffleTable[6561+1] = {
    592 lib/Target/ARM/ARMTargetTransformInfo.cpp:  unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
    593 lib/Target/ARM/ARMTargetTransformInfo.cpp:unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
    594 lib/Target/ARM/ARMTargetTransformInfo.cpp:  // We only handle costs of reverse shuffles for now.
    595 lib/Target/ARM/ARMTargetTransformInfo.cpp:    return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
    596 lib/Target/ARM/ARMTargetTransformInfo.cpp:  static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
    597 lib/Target/ARM/ARMTargetTransformInfo.cpp:    // Reverse shuffle cost one instruction if we are shuffling within a double
    598 lib/Target/ARM/ARMTargetTransformInfo.cpp:    // word (vrev) or two if we shuffle a quad word (vrev, vext).
    599 lib/Target/ARM/ARMTargetTransformInfo.cpp:  int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
    600 lib/Target/ARM/ARMTargetTransformInfo.cpp:    return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
    601 lib/Target/ARM/ARMTargetTransformInfo.cpp:  return LT.first * NEONShuffleTbl[Idx].Cost;
    602 lib/Target/CppBackend/CPPBackend.cpp:      case Instruction::ShuffleVector:  Out << "getShuffleVector("; break;
    603 lib/Target/CppBackend/CPPBackend.cpp:  case Instruction::ShuffleVector: {
    604 lib/Target/CppBackend/CPPBackend.cpp:    const ShuffleVectorInst* svi = cast<ShuffleVectorInst>(I);
    605 lib/Target/CppBackend/CPPBackend.cpp:    Out << "ShuffleVectorInst* " << getCppName(svi)
    606 lib/Target/CppBackend/CPPBackend.cpp:        << " = new ShuffleVectorInst(" << opNames[0]
    607 lib/Target/Hexagon/HexagonIntrinsics.td:// STYPE / PERM / Vector shuffle.
    608 lib/Target/Mips/MSA.txt:        It is not possible to emit vshf.w when the shuffle description is
    609 lib/Target/Mips/MSA.txt:        instead. It is also impossible for the shuffle description to be
    610 lib/Target/Mips/MSA.txt:        unknown at compile-time due to the definition of shufflevector in
    611 lib/Target/Mips/MSA.txt:        When the shuffle description describes a splat operation, splat.[bhwd]
    612 lib/Target/Mips/MSA.txt:        same shuffle. ilvev.d will be emitted instead.
    613 lib/Target/Mips/MSA.txt:        same shuffle. ilvod.d will be emitted instead.
    614 lib/Target/Mips/MipsISelLowering.h:      // Vector Shuffle with mask as an operand
    615 lib/Target/Mips/MipsISelLowering.h:      VSHF,  // Generic shuffle
    616 lib/Target/Mips/MipsISelLowering.h:      SHF,   // 4-element set shuffle.
    617 lib/Target/Mips/MipsMSAInstrInfo.td:// Big endian bitcasts expand to shuffle instructions.
    618 lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
    619 lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
    620 lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
    621 lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
    622 lib/Target/Mips/MipsSEISelLowering.cpp:    // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
    623 lib/Target/Mips/MipsSEISelLowering.cpp:// SHF splits the vector into blocks of four elements, then shuffles these
    624 lib/Target/Mips/MipsSEISelLowering.cpp://   %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
    625 lib/Target/Mips/MipsSEISelLowering.cpp:// This mostly consists of converting the shuffle indices in Indices into a
    626 lib/Target/Mips/MipsSEISelLowering.cpp:    llvm_unreachable("shuffle vector mask references neither vector operand?");
    627 lib/Target/Mips/MipsSEISelLowering.cpp:// indices in the shuffle.
    628 lib/Target/Mips/MipsSEISelLowering.cpp:  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
    629 lib/Target/Mips/MipsSEISelLowering.h:    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
    630 lib/Target/Mips/MipsSEISelLowering.h:    /// depending on the indices in the shuffle.
    631 lib/Target/NVPTX/NVPTX.h:  VecShuffle = 4,
    632 lib/Target/NVPTX/NVPTXGenericToNVVM.cpp:  case Instruction::ShuffleVector:
    633 lib/Target/NVPTX/NVPTXGenericToNVVM.cpp:    // ShuffleVector
    634 lib/Target/NVPTX/NVPTXGenericToNVVM.cpp:    return Builder.CreateShuffleVector(NewOperands[0], NewOperands[1],
    635 lib/Target/NVPTX/NVPTXInstrInfo.td:def isVecShuffle : VecInstTypeEnum<4>;
    636 lib/Target/NVPTX/NVPTXVector.td:class ShuffleOneLine<string vecsize, string elem, string type>
    637 lib/Target/NVPTX/NVPTXVector.td:class ShuffleAsmStr2<string type>
    638 lib/Target/NVPTX/NVPTXVector.td:  string t1 = ShuffleOneLine<"2", "0", type>.s;
    639 lib/Target/NVPTX/NVPTXVector.td:  string s  = !strconcat(t2, ShuffleOneLine<"2", "1", type>.s);
    640 lib/Target/NVPTX/NVPTXVector.td:class ShuffleAsmStr4<string type>
    641 lib/Target/NVPTX/NVPTXVector.td:  string t1 = ShuffleOneLine<"4", "0", type>.s;
    642 lib/Target/NVPTX/NVPTXVector.td:  string t3 = !strconcat(t2, ShuffleOneLine<"4", "1", type>.s);
    643 lib/Target/NVPTX/NVPTXVector.td:  string t5 = !strconcat(t4, ShuffleOneLine<"4", "2", type>.s);
    644 lib/Target/NVPTX/NVPTXVector.td:  string s  = !strconcat(t6, ShuffleOneLine<"4", "3", type>.s);
    645 lib/Target/NVPTX/NVPTXVector.td:let neverHasSideEffects=1, VecInstType=isVecShuffle.Value in {
    646 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4f32 : NVPTXVecInst<(outs V4F32Regs:$dst),
    647 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"f32">.s),
    648 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4i32 : NVPTXVecInst<(outs V4I32Regs:$dst),
    649 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"u32">.s),
    650 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4i16 : NVPTXVecInst<(outs V4I16Regs:$dst),
    651 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"u16">.s),
    652 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4i8 : NVPTXVecInst<(outs V4I8Regs:$dst),
    653 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"u16">.s),
    654 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2f32 : NVPTXVecInst<(outs V2F32Regs:$dst),
    655 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"f32">.s),
    656 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i32 : NVPTXVecInst<(outs V2I32Regs:$dst),
    657 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u32">.s),
    658 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i8 : NVPTXVecInst<(outs V2I8Regs:$dst),
    659 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u16">.s),
    660 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i16 : NVPTXVecInst<(outs V2I16Regs:$dst),
    661 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u16">.s),
    662 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2f64 : NVPTXVecInst<(outs V2F64Regs:$dst),
    663 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"f64">.s),
    664 lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i64 : NVPTXVecInst<(outs V2I64Regs:$dst),
    665 lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u64">.s),
    666 lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask0 : SDNodeXForm<vector_shuffle, [{
    667 lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
    668 lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask1 : SDNodeXForm<vector_shuffle, [{
    669 lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
    670 lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask2 : SDNodeXForm<vector_shuffle, [{
    671 lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
    672 lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask3 : SDNodeXForm<vector_shuffle, [{
    673 lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
    674 lib/Target/NVPTX/NVPTXVector.td:                       (vector_shuffle node:$lhs, node:$rhs),
    675 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2f64 V2F64Regs:$src1, V2F64Regs:$src2,
    676 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
    677 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4f32 V4F32Regs:$src1, V4F32Regs:$src2,
    678 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
    679 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
    680 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2f32 V2F32Regs:$src1, V2F32Regs:$src2,
    681 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
    682 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i64 V2I64Regs:$src1, V2I64Regs:$src2,
    683 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
    684 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4i32 V4I32Regs:$src1, V4I32Regs:$src2,
    685 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
    686 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
    687 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i32 V2I32Regs:$src1, V2I32Regs:$src2,
    688 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
    689 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4i16 V4I16Regs:$src1, V4I16Regs:$src2,
    690 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
    691 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
    692 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i16 V2I16Regs:$src1, V2I16Regs:$src2,
    693 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
    694 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4i8 V4I8Regs:$src1, V4I8Regs:$src2,
    695 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
    696 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
    697 lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i8 V2I8Regs:$src1, V2I8Regs:$src2,
    698 lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
    699 lib/Target/PowerPC/PPCISelLowering.cpp:#include "PPCPerfectShuffle.h"
    700 lib/Target/PowerPC/PPCISelLowering.cpp:      // We promote all shuffles to v16i8.
    701 lib/Target/PowerPC/PPCISelLowering.cpp:/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
    702 lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
    703 lib/Target/PowerPC/PPCISelLowering.cpp:/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
    704 lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
    705 lib/Target/PowerPC/PPCISelLowering.cpp:/// isVMerge - Common function, used to match vmrg* shuffles.
    706 lib/Target/PowerPC/PPCISelLowering.cpp:static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
    707 lib/Target/PowerPC/PPCISelLowering.cpp:         "PPC only supports shuffles by bytes!");
    708 lib/Target/PowerPC/PPCISelLowering.cpp:/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
    709 lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
    710 lib/Target/PowerPC/PPCISelLowering.cpp:/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
    711 lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
    712 lib/Target/PowerPC/PPCISelLowering.cpp:/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
    713 lib/Target/PowerPC/PPCISelLowering.cpp:int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
    714 lib/Target/PowerPC/PPCISelLowering.cpp:         "PPC only supports shuffles by bytes!");
    715 lib/Target/PowerPC/PPCISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
    716 lib/Target/PowerPC/PPCISelLowering.cpp:  // Find the first non-undef value in the shuffle mask.
    717 lib/Target/PowerPC/PPCISelLowering.cpp:/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
    718 lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
    719 lib/Target/PowerPC/PPCISelLowering.cpp:/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
    720 lib/Target/PowerPC/PPCISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
    721 lib/Target/PowerPC/PPCISelLowering.cpp:  assert(isSplatShuffleMask(SVOp, EltSize));
    722 lib/Target/PowerPC/PPCISelLowering.cpp:  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
    723 lib/Target/PowerPC/PPCISelLowering.cpp:/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
    724 lib/Target/PowerPC/PPCISelLowering.cpp:/// the specified operations to build the shuffle.
    725 lib/Target/PowerPC/PPCISelLowering.cpp:static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
    726 lib/Target/PowerPC/PPCISelLowering.cpp:  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
    727 lib/Target/PowerPC/PPCISelLowering.cpp:  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
    728 lib/Target/PowerPC/PPCISelLowering.cpp:  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
    729 lib/Target/PowerPC/PPCISelLowering.cpp:/// is a shuffle we can handle in a single instruction, return it.  Otherwise,
    730 lib/Target/PowerPC/PPCISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
    731 lib/Target/PowerPC/PPCISelLowering.cpp:    if (PPC::isSplatShuffleMask(SVOp, 1) ||
    732 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isSplatShuffleMask(SVOp, 2) ||
    733 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isSplatShuffleMask(SVOp, 4) ||
    734 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVPKUWUMShuffleMask(SVOp, true) ||
    735 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVPKUHUMShuffleMask(SVOp, true) ||
    736 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
    737 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
    738 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
    739 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
    740 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
    741 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
    742 lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
    743 lib/Target/PowerPC/PPCISelLowering.cpp:  // Altivec has a variety of "shuffle immediates" that take two vector inputs
    744 lib/Target/PowerPC/PPCISelLowering.cpp:  if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
    745 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVPKUHUMShuffleMask(SVOp, false) ||
    746 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
    747 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
    748 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
    749 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
    750 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
    751 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
    752 lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGHShuffleMask(SVOp, 4, false))
    753 lib/Target/PowerPC/PPCISelLowering.cpp:  // Check to see if this is a shuffle of 4-byte values.  If so, we can use our
    754 lib/Target/PowerPC/PPCISelLowering.cpp:  // perfect shuffle table to emit an optimal matching sequence.
    755 lib/Target/PowerPC/PPCISelLowering.cpp:  bool isFourElementShuffle = true;
    756 lib/Target/PowerPC/PPCISelLowering.cpp:  for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
    757 lib/Target/PowerPC/PPCISelLowering.cpp:        isFourElementShuffle = false;
    758 lib/Target/PowerPC/PPCISelLowering.cpp:        isFourElementShuffle = false;
    759 lib/Target/PowerPC/PPCISelLowering.cpp:  // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
    760 lib/Target/PowerPC/PPCISelLowering.cpp:  // perfect shuffle vector to determine if it is cost effective to do this as
    761 lib/Target/PowerPC/PPCISelLowering.cpp:  if (isFourElementShuffle) {
    762 lib/Target/PowerPC/PPCISelLowering.cpp:    // Compute the index in the perfect shuffle table.
    763 lib/Target/PowerPC/PPCISelLowering.cpp:    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
    764 lib/Target/PowerPC/PPCISelLowering.cpp:    // used (perhaps because there are multiple permutes with the same shuffle
    765 lib/Target/PowerPC/PPCISelLowering.cpp:    // As a compromise, we only emit discrete instructions if the shuffle can be
    766 lib/Target/PowerPC/PPCISelLowering.cpp:      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
    767 lib/Target/PowerPC/PPCISelLowering.cpp:    return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
    768 lib/Target/PowerPC/PPCISelLowering.h:    /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
    769 lib/Target/PowerPC/PPCISelLowering.h:    bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
    770 lib/Target/PowerPC/PPCISelLowering.h:    /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
    771 lib/Target/PowerPC/PPCISelLowering.h:    bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
    772 lib/Target/PowerPC/PPCISelLowering.h:    /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
    773 lib/Target/PowerPC/PPCISelLowering.h:    bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
    774 lib/Target/PowerPC/PPCISelLowering.h:    /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
    775 lib/Target/PowerPC/PPCISelLowering.h:    bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
    776 lib/Target/PowerPC/PPCISelLowering.h:    /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
    777 lib/Target/PowerPC/PPCISelLowering.h:    int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
    778 lib/Target/PowerPC/PPCISelLowering.h:    /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
    779 lib/Target/PowerPC/PPCISelLowering.h:    bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
    780 lib/Target/PowerPC/PPCISelLowering.h:    /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
    781 lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    782 lib/Target/PowerPC/PPCInstrAltivec.td:                              (vector_shuffle node:$lhs, node:$rhs), [{
    783 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
    784 lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    785 lib/Target/PowerPC/PPCInstrAltivec.td:                              (vector_shuffle node:$lhs, node:$rhs), [{
    786 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
    787 lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    788 lib/Target/PowerPC/PPCInstrAltivec.td:                                    (vector_shuffle node:$lhs, node:$rhs), [{
    789 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
    790 lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    791 lib/Target/PowerPC/PPCInstrAltivec.td:                                    (vector_shuffle node:$lhs, node:$rhs), [{
    792 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
    793 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    794 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
    795 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
    796 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    797 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
    798 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
    799 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    800 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
    801 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
    802 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    803 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
    804 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
    805 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    806 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
    807 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
    808 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    809 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
    810 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
    811 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    812 lib/Target/PowerPC/PPCInstrAltivec.td:                               (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
    813 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
    814 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    815 lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
    816 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
    817 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    818 lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
    819 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
    820 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    821 lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
    822 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
    823 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    824 lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
    825 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
    826 lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    827 lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
    828 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
    829 lib/Target/PowerPC/PPCInstrAltivec.td:def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
    830 lib/Target/PowerPC/PPCInstrAltivec.td:  return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
    831 lib/Target/PowerPC/PPCInstrAltivec.td:def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    832 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
    833 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVSLDOIShuffleMask(N, false) != -1;
    834 lib/Target/PowerPC/PPCInstrAltivec.td:/// vector_shuffle(X,undef,mask) by the dag combiner.
    835 lib/Target/PowerPC/PPCInstrAltivec.td:def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
    836 lib/Target/PowerPC/PPCInstrAltivec.td:  return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
    837 lib/Target/PowerPC/PPCInstrAltivec.td:def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    838 lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
    839 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVSLDOIShuffleMask(N, true) != -1;
    840 lib/Target/PowerPC/PPCInstrAltivec.td:// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
    841 lib/Target/PowerPC/PPCInstrAltivec.td:def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
    842 lib/Target/PowerPC/PPCInstrAltivec.td:def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    843 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
    844 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
    845 lib/Target/PowerPC/PPCInstrAltivec.td:def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
    846 lib/Target/PowerPC/PPCInstrAltivec.td:def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    847 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
    848 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
    849 lib/Target/PowerPC/PPCInstrAltivec.td:def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
    850 lib/Target/PowerPC/PPCInstrAltivec.td:def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
    851 lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
    852 lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
    853 lib/Target/PowerPC/PPCInstrAltivec.td:// Shuffles.
    854 lib/Target/PowerPC/PPCInstrAltivec.td:                         (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
    855 lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
    856 lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
    857 lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
    858 lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
    859 lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
    860 lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
    861 lib/Target/PowerPC/PPCInstrAltivec.td:                        (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
    862 lib/Target/PowerPC/PPCInstrAltivec.td:                        (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
    863 lib/Target/PowerPC/PPCInstrAltivec.td:                        (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
    864 lib/Target/PowerPC/PPCInstrAltivec.td:                         (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
    865 lib/Target/PowerPC/PPCInstrAltivec.td:                         (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
    866 lib/Target/PowerPC/PPCInstrAltivec.td:// Shuffles.
    867 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
    868 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
    869 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
    870 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
    871 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
    872 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
    873 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
    874 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
    875 lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
    876 lib/Target/PowerPC/PPCPerfectShuffle.h://===-- PPCPerfectShuffle.h - Altivec Perfect Shuffle Table -----*- C++ -*-===//
    877 lib/Target/PowerPC/PPCPerfectShuffle.h:// This file, which was autogenerated by llvm-PerfectShuffle, contains data
    878 lib/Target/PowerPC/PPCPerfectShuffle.h:// for the optimal way to build a perfect shuffle without using vperm.
    879 lib/Target/PowerPC/PPCPerfectShuffle.h:static const unsigned PerfectShuffleTable[6561+1] = {
    880 lib/Target/PowerPC/PPCTargetTransformInfo.cpp:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
    881 lib/Target/PowerPC/PPCTargetTransformInfo.cpp:unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
    882 lib/Target/PowerPC/PPCTargetTransformInfo.cpp:  return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
    883 lib/Target/PowerPC/README.txt:argument bytes for r4 and r5. The trick then would be to shuffle the argument
    884 lib/Target/R600/R600TextureIntrinsicsReplacer.cpp:        Builder.CreateShuffleVector(Coord, Coord, SwizzleMask);
    885 lib/Target/Sparc/SparcInstrVIS.td:def BSHUFFLE  : VISInst<0b000011100, "bshuffle">;
    886 lib/Target/X86/README-FPStack.txt:The FP stackifier should handle simple permutates to reduce number of shuffle
    887 lib/Target/X86/README-SSE.txt:small table + unaligned load + shuffle instead of going through memory.
    888 lib/Target/X86/README-SSE.txt:  return _mm_shuffle_epi8(value,
    889 lib/Target/X86/README-SSE.txt:Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}.
    890 lib/Target/X86/README-SSE.txt:This can be used to simplify a variety of shuffle operations, where the
    891 lib/Target/X86/README-SSE.txt:We should transform a shuffle of two vectors of constants into a single vector
    892 lib/Target/X86/README-SSE.txt:doing a shuffle from v[1] to v[0] then a float store.
    893 lib/Target/X86/X86FloatingPoint.cpp:    // Shuffle live registers to match the expectations of successor blocks.
    894 lib/Target/X86/X86FloatingPoint.cpp:    /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
    895 lib/Target/X86/X86FloatingPoint.cpp:    void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
    896 lib/Target/X86/X86FloatingPoint.cpp:/// MBB. Shuffle live registers to match the expected fixed stack of any
    897 lib/Target/X86/X86FloatingPoint.cpp:  // FIXME: This can probably be combined with the shuffle below.
    898 lib/Target/X86/X86FloatingPoint.cpp:    shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
    899 lib/Target/X86/X86FloatingPoint.cpp:/// shuffleStackTop - emit fxch instructions before I to shuffle the top
    900 lib/Target/X86/X86FloatingPoint.cpp:void FPS::shuffleStackTop(const unsigned char *FixStack,
    901 lib/Target/X86/X86FloatingPoint.cpp:    shuffleStackTop(PendingST, NumPendingSTs, I);
    902 lib/Target/X86/X86ISelDAGToDAG.cpp:  // elements.  This is a vector shuffle from the zero vector.
    903 lib/Target/X86/X86ISelLowering.cpp:#include "Utils/X86ShuffleDecode.h"
    904 lib/Target/X86/X86ISelLowering.cpp:    // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
    905 lib/Target/X86/X86ISelLowering.cpp:static bool isTargetShuffle(unsigned Opcode) {
    906 lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
    907 lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
    908 lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
    909 lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
    910 lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
    911 lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
    912 lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
    913 lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
    914 lib/Target/X86/X86ISelLowering.cpp:/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
    915 lib/Target/X86/X86ISelLowering.cpp:/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
    916 lib/Target/X86/X86ISelLowering.cpp:  // Upper quadword shuffled.
    917 lib/Target/X86/X86ISelLowering.cpp:    // Upper quadword shuffled.
    918 lib/Target/X86/X86ISelLowering.cpp:/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
    919 lib/Target/X86/X86ISelLowering.cpp:  // Lower quadword shuffled.
    920 lib/Target/X86/X86ISelLowering.cpp:    // Lower quadword shuffled.
    921 lib/Target/X86/X86ISelLowering.cpp:/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
    922 lib/Target/X86/X86ISelLowering.cpp:  // Do not handle 64-bit element shuffles with palignr.
    923 lib/Target/X86/X86ISelLowering.cpp:/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
    924 lib/Target/X86/X86ISelLowering.cpp:static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
    925 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to 128/256-bit
    926 lib/Target/X86/X86ISelLowering.cpp:/// reverse of what x86 shuffles want.
    927 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
    928 lib/Target/X86/X86ISelLowering.cpp:/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
    929 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
    930 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVLHPS.
    931 lib/Target/X86/X86ISelLowering.cpp:SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
    932 lib/Target/X86/X86ISelLowering.cpp:    Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
    933 lib/Target/X86/X86ISelLowering.cpp:    Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
    934 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
    935 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to UNPCKL.
    936 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to UNPCKH.
    937 lib/Target/X86/X86ISelLowering.cpp:/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
    938 lib/Target/X86/X86ISelLowering.cpp:/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
    939 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVSS,
    940 lib/Target/X86/X86ISelLowering.cpp:/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
    941 lib/Target/X86/X86ISelLowering.cpp:/// shuffle bellow:
    942 lib/Target/X86/X86ISelLowering.cpp:///   vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
    943 lib/Target/X86/X86ISelLowering.cpp:  // The shuffle result is divided into half A and half B. In total the two
    944 lib/Target/X86/X86ISelLowering.cpp:/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
    945 lib/Target/X86/X86ISelLowering.cpp:static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
    946 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
    947 lib/Target/X86/X86ISelLowering.cpp:/// In VPERMILPD the two lanes could be shuffled independently of each other
    948 lib/Target/X86/X86ISelLowering.cpp:/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
    949 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
    950 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
    951 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to 256-bit
    952 lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to 128-bit
    953 lib/Target/X86/X86ISelLowering.cpp:/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
    954 lib/Target/X86/X86ISelLowering.cpp:static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
    955 lib/Target/X86/X86ISelLowering.cpp:/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
    956 lib/Target/X86/X86ISelLowering.cpp:static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
    957 lib/Target/X86/X86ISelLowering.cpp:/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
    958 lib/Target/X86/X86ISelLowering.cpp:static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
    959 lib/Target/X86/X86ISelLowering.cpp:/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
    960 lib/Target/X86/X86ISelLowering.cpp:static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
    961 lib/Target/X86/X86ISelLowering.cpp:/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
    962 lib/Target/X86/X86ISelLowering.cpp:static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
    963 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
    964 lib/Target/X86/X86ISelLowering.cpp:/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
    965 lib/Target/X86/X86ISelLowering.cpp:/// FIXME: move to dag combiner / method on ShuffleVectorSDNode
    966 lib/Target/X86/X86ISelLowering.cpp:static bool isZeroShuffle(ShuffleVectorSDNode *N) {
    967 lib/Target/X86/X86ISelLowering.cpp:/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
    968 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
    969 lib/Target/X86/X86ISelLowering.cpp:/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
    970 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
    971 lib/Target/X86/X86ISelLowering.cpp:/// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
    972 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
    973 lib/Target/X86/X86ISelLowering.cpp:// a generic shuffle instruction because the target has no such instructions.
    974 lib/Target/X86/X86ISelLowering.cpp:// Generate shuffles which repeat i16 and i8 several times until they can be
    975 lib/Target/X86/X86ISelLowering.cpp:// represented by v4f32 and then be manipulated by target suported shuffles.
    976 lib/Target/X86/X86ISelLowering.cpp:/// getLegalSplat - Generate a legal splat with supported x86 shuffles
    977 lib/Target/X86/X86ISelLowering.cpp:    V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
    978 lib/Target/X86/X86ISelLowering.cpp:    V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
    979 lib/Target/X86/X86ISelLowering.cpp:/// PromoteSplat - Splat is promoted to target supported vector shuffles.
    980 lib/Target/X86/X86ISelLowering.cpp:static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
    981 lib/Target/X86/X86ISelLowering.cpp:  // All i16 and i8 vector types can't be used directly by a generic shuffle
    982 lib/Target/X86/X86ISelLowering.cpp:  // instruction because the target has no such instruction. Generate shuffles
    983 lib/Target/X86/X86ISelLowering.cpp:  // be manipulated by target suported shuffles.
    984 lib/Target/X86/X86ISelLowering.cpp:  // to use VPERM* to shuffle the vectors
    985 lib/Target/X86/X86ISelLowering.cpp:/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
    986 lib/Target/X86/X86ISelLowering.cpp:/// vector of zero or undef vector.  This produces a shuffle where the low
    987 lib/Target/X86/X86ISelLowering.cpp:/// Idx.  This produces a shuffle mask like 4,1,2,3 (idx=0) or  0,1,2,4 (idx=3).
    988 lib/Target/X86/X86ISelLowering.cpp:static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
    989 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
    990 lib/Target/X86/X86ISelLowering.cpp:/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
    991 lib/Target/X86/X86ISelLowering.cpp:static bool getTargetShuffleMask(SDNode *N, MVT VT,
    992 lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("unknown target shuffle node");
    993 lib/Target/X86/X86ISelLowering.cpp:/// getShuffleScalarElt - Returns the scalar element that will make up the ith
    994 lib/Target/X86/X86ISelLowering.cpp:/// element of the result of the vector shuffle.
    995 lib/Target/X86/X86ISelLowering.cpp:static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
    996 lib/Target/X86/X86ISelLowering.cpp:  if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
    997 lib/Target/X86/X86ISelLowering.cpp:    return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
    998 lib/Target/X86/X86ISelLowering.cpp:  // Recurse into target specific vector shuffles to find scalars.
    999 lib/Target/X86/X86ISelLowering.cpp:  if (isTargetShuffle(Opcode)) {
    1000 lib/Target/X86/X86ISelLowering.cpp:    SmallVector<int, 16> ShuffleMask;
    1001 lib/Target/X86/X86ISelLowering.cpp:    if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
    1002 lib/Target/X86/X86ISelLowering.cpp:    int Elt = ShuffleMask[Index];
    1003 lib/Target/X86/X86ISelLowering.cpp:    return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
    1004 lib/Target/X86/X86ISelLowering.cpp:/// shuffle operation which come from a consecutively from a zero. The
    1005 lib/Target/X86/X86ISelLowering.cpp:static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
    1006 lib/Target/X86/X86ISelLowering.cpp:    SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
    1007 lib/Target/X86/X86ISelLowering.cpp:/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
    1008 lib/Target/X86/X86ISelLowering.cpp:bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
    1009 lib/Target/X86/X86ISelLowering.cpp:/// isVectorShiftRight - Returns true if the shuffle can be implemented as a
    1010 lib/Target/X86/X86ISelLowering.cpp:static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
    1011 lib/Target/X86/X86ISelLowering.cpp:  //   vector_shuffle V1, V2 <1, 2, 3, X>
    1012 lib/Target/X86/X86ISelLowering.cpp:  if (!isShuffleMaskConsecutive(SVOp,
    1013 lib/Target/X86/X86ISelLowering.cpp:/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
    1014 lib/Target/X86/X86ISelLowering.cpp:static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
    1015 lib/Target/X86/X86ISelLowering.cpp:  //   vector_shuffle V1, V2 <X, X, 4, 5>
    1016 lib/Target/X86/X86ISelLowering.cpp:  if (!isShuffleMaskConsecutive(SVOp,
    1017 lib/Target/X86/X86ISelLowering.cpp:/// isVectorShift - Returns true if the shuffle can be implemented as a
    1018 lib/Target/X86/X86ISelLowering.cpp:static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
    1019 lib/Target/X86/X86ISelLowering.cpp:  // the shuffle mask.
    1020 lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
    1021 lib/Target/X86/X86ISelLowering.cpp:/// 2. A splat shuffle which uses a scalar_to_vector node which comes from
    1022 lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
    1023 lib/Target/X86/X86ISelLowering.cpp:      // Shuffles must have a splat mask where the first element is
    1024 lib/Target/X86/X86ISelLowering.cpp:static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
    1025 lib/Target/X86/X86ISelLowering.cpp:        // Quit if more than 2 vectors to shuffle
    1026 lib/Target/X86/X86ISelLowering.cpp:  SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
    1027 lib/Target/X86/X86ISelLowering.cpp:    // a constant pool load than it is to do a movd + shuffle.
    1028 lib/Target/X86/X86ISelLowering.cpp:        // convert it to a vector with movd (S2V+shuffle to zero extend).
    1029 lib/Target/X86/X86ISelLowering.cpp:        Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
    1030 lib/Target/X86/X86ISelLowering.cpp:          Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
    1031 lib/Target/X86/X86ISelLowering.cpp:    // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
    1032 lib/Target/X86/X86ISelLowering.cpp:        return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
    1033 lib/Target/X86/X86ISelLowering.cpp:          Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
    1034 lib/Target/X86/X86ISelLowering.cpp:    // movd/movss) to move this into the low element, then shuffle it into
    1035 lib/Target/X86/X86ISelLowering.cpp:      // Turn it into a shuffle of zero and zero-extended scalar to vector.
    1036 lib/Target/X86/X86ISelLowering.cpp:      Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
    1037 lib/Target/X86/X86ISelLowering.cpp:      return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
    1038 lib/Target/X86/X86ISelLowering.cpp:  // Splat is obviously ok. Let legalizer expand it to a shuffle.
    1039 lib/Target/X86/X86ISelLowering.cpp:      // Instead of a shuffle like this:
    1040 lib/Target/X86/X86ISelLowering.cpp:      // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
    1041 lib/Target/X86/X86ISelLowering.cpp:      // shuffle (vload ptr)), undef, <1, 1, 1, 1>
    1042 lib/Target/X86/X86ISelLowering.cpp:  // shuffles to put them in place.
    1043 lib/Target/X86/X86ISelLowering.cpp:      return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
    1044 lib/Target/X86/X86ISelLowering.cpp:  // If element VT is == 32 bits, turn it into a number of shuffles.
    1045 lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
    1046 lib/Target/X86/X86ISelLowering.cpp:    // Check for a build vector from mostly shuffle plus few inserting.
    1047 lib/Target/X86/X86ISelLowering.cpp:    SDValue Sh = buildFromShuffleMostly(Op, DAG);
    1048 lib/Target/X86/X86ISelLowering.cpp:        // then it is safe to just drop this shuffle: V[i] is already in the
    1049 lib/Target/X86/X86ISelLowering.cpp:// Try to lower a shuffle node into a simple blend instruction.
    1050 lib/Target/X86/X86ISelLowering.cpp:LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
    1051 lib/Target/X86/X86ISelLowering.cpp:// v8i16 shuffles - Prefer shuffles in the following order:
    1052 lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
    1053 lib/Target/X86/X86ISelLowering.cpp:  // of the two input vectors, shuffle them into one input vector so only a
    1054 lib/Target/X86/X86ISelLowering.cpp:  // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
    1055 lib/Target/X86/X86ISelLowering.cpp:  // the shuffle mask.  If a quad is scored as -1, that means that it contains
    1056 lib/Target/X86/X86ISelLowering.cpp:    NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
    1057 lib/Target/X86/X86ISelLowering.cpp:    // source words for the shuffle, to aid later transformations.
    1058 lib/Target/X86/X86ISelLowering.cpp:    // pshufhw, that's as cheap as it gets.  Return the new shuffle.
    1059 lib/Target/X86/X86ISelLowering.cpp:      NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
    1060 lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
    1061 lib/Target/X86/X86ISelLowering.cpp:      TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
    1062 lib/Target/X86/X86ISelLowering.cpp:                             getShufflePSHUFLWImmediate(SVOp);
    1063 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
    1064 lib/Target/X86/X86ISelLowering.cpp:    // shuffle mask element to zero out elements that come from V2 in the V1
    1065 lib/Target/X86/X86ISelLowering.cpp:    // Calculate the shuffle mask for the second input, shuffle it, and
    1066 lib/Target/X86/X86ISelLowering.cpp:    // OR it with the first shuffled input.
    1067 lib/Target/X86/X86ISelLowering.cpp:    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
    1068 lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
    1069 lib/Target/X86/X86ISelLowering.cpp:      NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
    1070 lib/Target/X86/X86ISelLowering.cpp:                                  getShufflePSHUFLWImmediate(SVOp), DAG);
    1071 lib/Target/X86/X86ISelLowering.cpp:    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
    1072 lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
    1073 lib/Target/X86/X86ISelLowering.cpp:      NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
    1074 lib/Target/X86/X86ISelLowering.cpp:                                  getShufflePSHUFHWImmediate(SVOp), DAG);
    1075 lib/Target/X86/X86ISelLowering.cpp:// v16i8 shuffles - Prefer shuffles in the following order:
    1076 lib/Target/X86/X86ISelLowering.cpp:// 3. [all]   v8i16 shuffle + N x pextrw + rotate + pinsrw
    1077 lib/Target/X86/X86ISelLowering.cpp:static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
    1078 lib/Target/X86/X86ISelLowering.cpp:    // Calculate the shuffle mask for the second input, shuffle it, and
    1079 lib/Target/X86/X86ISelLowering.cpp:    // OR it with the first shuffled input.
    1080 lib/Target/X86/X86ISelLowering.cpp:// v32i8 shuffles - Translate to VPSHUFB if possible.
    1081 lib/Target/X86/X86ISelLowering.cpp:SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
    1082 lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(MaskVals, 32);
    1083 lib/Target/X86/X86ISelLowering.cpp:/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
    1084 lib/Target/X86/X86ISelLowering.cpp:/// done when every pair / quad of shuffle mask elements point to elements in
    1085 lib/Target/X86/X86ISelLowering.cpp:/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
    1086 lib/Target/X86/X86ISelLowering.cpp:SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
    1087 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
    1088 lib/Target/X86/X86ISelLowering.cpp:/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
    1089 lib/Target/X86/X86ISelLowering.cpp:/// which could not be matched by any known target speficic shuffle
    1090 lib/Target/X86/X86ISelLowering.cpp:LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
    1091 lib/Target/X86/X86ISelLowering.cpp:  SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
    1092 lib/Target/X86/X86ISelLowering.cpp:    // Build a shuffle mask for the output, discovering on the fly which
    1093 lib/Target/X86/X86ISelLowering.cpp:    // input vectors to use as shuffle operands (recorded in InputUsed).
    1094 lib/Target/X86/X86ISelLowering.cpp:    // If building a suitable shuffle vector proves too hard, then bail
    1095 lib/Target/X86/X86ISelLowering.cpp:      // Find or create a shuffle vector operand to hold this input.
    1096 lib/Target/X86/X86ISelLowering.cpp:        // shuffle vector.  Insert all elements into a BUILD_VECTOR instead.
    1097 lib/Target/X86/X86ISelLowering.cpp:      // Add the mask index for the new shuffle vector.
    1098 lib/Target/X86/X86ISelLowering.cpp:      // At least one input vector was used. Create a new shuffle vector.
    1099 lib/Target/X86/X86ISelLowering.cpp:      Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
    1100 lib/Target/X86/X86ISelLowering.cpp:/// 4 elements, and match them with several different shuffle types.
    1101 lib/Target/X86/X86ISelLowering.cpp:LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
    1102 lib/Target/X86/X86ISelLowering.cpp:    // implemented with two shuffles. First shuffle gather the elements.
    1103 lib/Target/X86/X86ISelLowering.cpp:    // The second shuffle, which takes the first shuffle as both of its
    1104 lib/Target/X86/X86ISelLowering.cpp:    V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
    1105 lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
    1106 lib/Target/X86/X86ISelLowering.cpp:      CommuteVectorShuffleMask(PermMask, 4);
    1107 lib/Target/X86/X86ISelLowering.cpp:    V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
    1108 lib/Target/X86/X86ISelLowering.cpp:      return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
    1109 lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
    1110 lib/Target/X86/X86ISelLowering.cpp:  // Break it into (shuffle shuffle_hi, shuffle_lo).
    1111 lib/Target/X86/X86ISelLowering.cpp:  SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
    1112 lib/Target/X86/X86ISelLowering.cpp:  SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
    1113 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
    1114 lib/Target/X86/X86ISelLowering.cpp:                     getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
    1115 lib/Target/X86/X86ISelLowering.cpp:  assert(VT != MVT::v2i64 && "unsupported shuffle type");
    1116 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
    1117 lib/Target/X86/X86ISelLowering.cpp:                     getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
    1118 lib/Target/X86/X86ISelLowering.cpp:         "unsupported shuffle type");
    1119 lib/Target/X86/X86ISelLowering.cpp:  return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
    1120 lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
    1121 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
    1122 lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
    1123 lib/Target/X86/X86ISelLowering.cpp:  // this is horrible, but will stay like this until we move all shuffle
    1124 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
    1125 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
    1126 lib/Target/X86/X86ISelLowering.cpp:  assert(VT != MVT::v4i32 && "unsupported shuffle type");
    1127 lib/Target/X86/X86ISelLowering.cpp:  return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
    1128 lib/Target/X86/X86ISelLowering.cpp:                              getShuffleSHUFImmediate(SVOp), DAG);
    1129 lib/Target/X86/X86ISelLowering.cpp:// Reduce a vector shuffle to zext.
    1130 lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
    1131 lib/Target/X86/X86ISelLowering.cpp:  // Check the shuffle mask.
    1132 lib/Target/X86/X86ISelLowering.cpp:  // Simplify the operand as it's prepared to be fed into shuffle.
    1133 lib/Target/X86/X86ISelLowering.cpp:NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
    1134 lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
    1135 lib/Target/X86/X86ISelLowering.cpp:  if (isZeroShuffle(SVOp))
    1136 lib/Target/X86/X86ISelLowering.cpp:  // Check integer expanding shuffles.
    1137 lib/Target/X86/X86ISelLowering.cpp:  // If the shuffle can be profitably rewritten as a narrower shuffle, then
    1138 lib/Target/X86/X86ISelLowering.cpp:    SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
    1139 lib/Target/X86/X86ISelLowering.cpp:      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
    1140 lib/Target/X86/X86ISelLowering.cpp:        if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
    1141 lib/Target/X86/X86ISelLowering.cpp:      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
    1142 lib/Target/X86/X86ISelLowering.cpp:        if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
    1143 lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
    1144 lib/Target/X86/X86ISelLowering.cpp:  assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
    1145 lib/Target/X86/X86ISelLowering.cpp:  // When we create a shuffle node we put the UNDEF node to second operand,
    1146 lib/Target/X86/X86ISelLowering.cpp:    return CommuteVectorShuffle(SVOp, DAG);
    1147 lib/Target/X86/X86ISelLowering.cpp:  // Vector shuffle lowering takes 3 steps:
    1148 lib/Target/X86/X86ISelLowering.cpp:  // 2) Matching of shuffles with known shuffle masks to x86 target specific
    1149 lib/Target/X86/X86ISelLowering.cpp:  //    shuffle nodes.
    1150 lib/Target/X86/X86ISelLowering.cpp:  // 3) Rewriting of unmatched masks into new generic shuffle operations,
    1151 lib/Target/X86/X86ISelLowering.cpp:  //    so the shuffle can be broken into other shuffles and the legalizer can
    1152 lib/Target/X86/X86ISelLowering.cpp:  // The general idea is that no vector_shuffle operation should be left to
    1153 lib/Target/X86/X86ISelLowering.cpp:  SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
    1154 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
    1155 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
    1156 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
    1157 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
    1158 lib/Target/X86/X86ISelLowering.cpp:    unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
    1159 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
    1160 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
    1161 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
    1162 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
    1163 lib/Target/X86/X86ISelLowering.cpp:                                getShufflePALIGNRImmediate(SVOp),
    1164 lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
    1165 lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
    1166 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
    1167 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
    1168 lib/Target/X86/X86ISelLowering.cpp:    return CommuteVectorShuffle(SVOp, DAG);
    1169 lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(M, NumElems);
    1170 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
    1171 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
    1172 lib/Target/X86/X86ISelLowering.cpp:    // new vector_shuffle with the corrected mask.p
    1173 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
    1174 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
    1175 lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(M, NumElems);
    1176 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
    1177 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
    1178 lib/Target/X86/X86ISelLowering.cpp:  // Normalize the node to match x86 shuffle ops if needed
    1179 lib/Target/X86/X86ISelLowering.cpp:    return CommuteVectorShuffle(SVOp, DAG);
    1180 lib/Target/X86/X86ISelLowering.cpp:  // The checks below are all present in isShuffleMaskLegal, but they are
    1181 lib/Target/X86/X86ISelLowering.cpp:  if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
    1182 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
    1183 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
    1184 lib/Target/X86/X86ISelLowering.cpp:                                getShufflePSHUFHWImmediate(SVOp),
    1185 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
    1186 lib/Target/X86/X86ISelLowering.cpp:                                getShufflePSHUFLWImmediate(SVOp),
    1187 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
    1188 lib/Target/X86/X86ISelLowering.cpp:                                getShuffleSHUFImmediate(SVOp), DAG);
    1189 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
    1190 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
    1191 lib/Target/X86/X86ISelLowering.cpp:  // Generate target specific nodes for 128 or 256-bit shuffles only
    1192 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
    1193 lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
    1194 lib/Target/X86/X86ISelLowering.cpp:                                  getShuffleSHUFImmediate(SVOp), DAG);
    1195 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
    1196 lib/Target/X86/X86ISelLowering.cpp:                                getShuffleSHUFImmediate(SVOp), DAG);
    1197 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
    1198 lib/Target/X86/X86ISelLowering.cpp:                                V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
    1199 lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
    1200 lib/Target/X86/X86ISelLowering.cpp:  // Since no target specific shuffle was selected for this generic one,
    1201 lib/Target/X86/X86ISelLowering.cpp:  // lower it into other known shuffles. FIXME: this isn't true yet, but
    1202 lib/Target/X86/X86ISelLowering.cpp:  // several different shuffle types.
    1203 lib/Target/X86/X86ISelLowering.cpp:  // Handle general 256-bit shuffles
    1204 lib/Target/X86/X86ISelLowering.cpp:    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
    1205 lib/Target/X86/X86ISelLowering.cpp:    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
    1206 lib/Target/X86/X86ISelLowering.cpp:    SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
    1207 lib/Target/X86/X86ISelLowering.cpp:                         DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
    1208 lib/Target/X86/X86ISelLowering.cpp:  Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
    1209 lib/Target/X86/X86ISelLowering.cpp:      In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
    1210 lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
    1211 lib/Target/X86/X86ISelLowering.cpp:      In = DAG.getVectorShuffle(MVT::v4i64, DL,  In, DAG.getUNDEF(MVT::v4i64),
    1212 lib/Target/X86/X86ISelLowering.cpp:    OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
    1213 lib/Target/X86/X86ISelLowering.cpp:    OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
    1214 lib/Target/X86/X86ISelLowering.cpp:    SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
    1215 lib/Target/X86/X86ISelLowering.cpp:  // Handle truncation of V256 to V128 using shuffles.
    1216 lib/Target/X86/X86ISelLowering.cpp:  // Prepare truncation shuffle mask
    1217 lib/Target/X86/X86ISelLowering.cpp:  SDValue V = DAG.getVectorShuffle(NVT, DL,
    1218 lib/Target/X86/X86ISelLowering.cpp:      SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
    1219 lib/Target/X86/X86ISelLowering.cpp:      SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
    1220 lib/Target/X86/X86ISelLowering.cpp:      SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
    1221 lib/Target/X86/X86ISelLowering.cpp:      SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
    1222 lib/Target/X86/X86ISelLowering.cpp:  // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
    1223 lib/Target/X86/X86ISelLowering.cpp:  SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
    1224 lib/Target/X86/X86ISelLowering.cpp:  SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
    1225 lib/Target/X86/X86ISelLowering.cpp:  // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
    1226 lib/Target/X86/X86ISelLowering.cpp:    SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
    1227 lib/Target/X86/X86ISelLowering.cpp:    SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
    1228 lib/Target/X86/X86ISelLowering.cpp:    // Merge the two vectors back together with a shuffle. This expands into 2
    1229 lib/Target/X86/X86ISelLowering.cpp:    // shuffles.
    1230 lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
    1231 lib/Target/X86/X86ISelLowering.cpp:               cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
    1232 lib/Target/X86/X86ISelLowering.cpp:               cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
    1233 lib/Target/X86/X86ISelLowering.cpp:/// isShuffleMaskLegal - Targets can use this to indicate that they only
    1234 lib/Target/X86/X86ISelLowering.cpp:X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
    1235 lib/Target/X86/X86ISelLowering.cpp:          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
    1236 lib/Target/X86/X86ISelLowering.cpp:/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
    1237 lib/Target/X86/X86ISelLowering.cpp:static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
    1238 lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
    1239 lib/Target/X86/X86ISelLowering.cpp:/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
    1240 lib/Target/X86/X86ISelLowering.cpp:static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
    1241 lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
    1242 lib/Target/X86/X86ISelLowering.cpp:/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
    1243 lib/Target/X86/X86ISelLowering.cpp:static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
    1244 lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
    1245 lib/Target/X86/X86ISelLowering.cpp:    // To match the shuffle mask, the first half of the mask should
    1246 lib/Target/X86/X86ISelLowering.cpp:  // Combine some shuffles into subvector extracts and inserts:
    1247 lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
    1248 lib/Target/X86/X86ISelLowering.cpp:  if (isShuffleHigh128VectorInsertLow(SVOp)) {
    1249 lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
    1250 lib/Target/X86/X86ISelLowering.cpp:  if (isShuffleLow128VectorInsertHigh(SVOp)) {
    1251 lib/Target/X86/X86ISelLowering.cpp:/// PerformShuffleCombine - Performs several different shuffle combines.
    1252 lib/Target/X86/X86ISelLowering.cpp:static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
    1253 lib/Target/X86/X86ISelLowering.cpp:  // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
    1254 lib/Target/X86/X86ISelLowering.cpp:    return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
    1255 lib/Target/X86/X86ISelLowering.cpp:  // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
    1256 lib/Target/X86/X86ISelLowering.cpp:    Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
    1257 lib/Target/X86/X86ISelLowering.cpp:/// a sequence of vector shuffle operations.
    1258 lib/Target/X86/X86ISelLowering.cpp:/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
    1259 lib/Target/X86/X86ISelLowering.cpp:/// specific shuffle of a load can be folded into a single element load.
    1260 lib/Target/X86/X86ISelLowering.cpp:/// shuffles have been customed lowered so we need to handle those here.
    1261 lib/Target/X86/X86ISelLowering.cpp:static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
    1262 lib/Target/X86/X86ISelLowering.cpp:  bool HasShuffleIntoBitcast = false;
    1263 lib/Target/X86/X86ISelLowering.cpp:    HasShuffleIntoBitcast = true;
    1264 lib/Target/X86/X86ISelLowering.cpp:  if (!isTargetShuffle(InVec.getOpcode()))
    1265 lib/Target/X86/X86ISelLowering.cpp:  SmallVector<int, 16> ShuffleMask;
    1266 lib/Target/X86/X86ISelLowering.cpp:  bool UnaryShuffle;
    1267 lib/Target/X86/X86ISelLowering.cpp:  if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
    1268 lib/Target/X86/X86ISelLowering.cpp:                            UnaryShuffle))
    1269 lib/Target/X86/X86ISelLowering.cpp:  int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
    1270 lib/Target/X86/X86ISelLowering.cpp:  // If inputs to shuffle are the same for both ops, then allow 2 uses
    1271 lib/Target/X86/X86ISelLowering.cpp:  if (HasShuffleIntoBitcast) {
    1272 lib/Target/X86/X86ISelLowering.cpp:    // If there's a bitcast before the shuffle, check if the load type and
    1273 lib/Target/X86/X86ISelLowering.cpp:  // All checks match so transform back to vector_shuffle so that DAG combiner
    1274 lib/Target/X86/X86ISelLowering.cpp:  // Create shuffle node taking into account the case that its a unary shuffle
    1275 lib/Target/X86/X86ISelLowering.cpp:  SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
    1276 lib/Target/X86/X86ISelLowering.cpp:  Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
    1277 lib/Target/X86/X86ISelLowering.cpp:                                 InVec.getOperand(0), Shuffle,
    1278 lib/Target/X86/X86ISelLowering.cpp:                                 &ShuffleMask[0]);
    1279 lib/Target/X86/X86ISelLowering.cpp:  Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
    1280 lib/Target/X86/X86ISelLowering.cpp:  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
    1281 lib/Target/X86/X86ISelLowering.cpp:/// generation and convert it from being a bunch of shuffles and extracts
    1282 lib/Target/X86/X86ISelLowering.cpp:  SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
    1283 lib/Target/X86/X86ISelLowering.cpp:          return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
    1284 lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
    1285 lib/Target/X86/X86ISelLowering.cpp:          SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
    1286 lib/Target/X86/X86ISelLowering.cpp:  // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
    1287 lib/Target/X86/X86ISelLowering.cpp:  // emit a shuffle and a arithmetic shift.
    1288 lib/Target/X86/X86ISelLowering.cpp:  // during the shuffle phase or after the shuffle.
    1289 lib/Target/X86/X86ISelLowering.cpp:    // We can't shuffle using an illegal type.
    1290 lib/Target/X86/X86ISelLowering.cpp:      // Otherwise we'll shuffle the small elements in the high bits of the
    1291 lib/Target/X86/X86ISelLowering.cpp:      SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
    1292 lib/Target/X86/X86ISelLowering.cpp:        ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
    1293 lib/Target/X86/X86ISelLowering.cpp:      SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
    1294 lib/Target/X86/X86ISelLowering.cpp:                                           &ShuffleVec[0]);
    1295 lib/Target/X86/X86ISelLowering.cpp:    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
    1296 lib/Target/X86/X86ISelLowering.cpp:      ShuffleVec[i*SizeRatio] = i;
    1297 lib/Target/X86/X86ISelLowering.cpp:    SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
    1298 lib/Target/X86/X86ISelLowering.cpp:                                         &ShuffleVec[0]);
    1299 lib/Target/X86/X86ISelLowering.cpp:  // Optimize trunc store (of multiple scalars) to shuffle and store.
    1300 lib/Target/X86/X86ISelLowering.cpp:    // Create a type on which we perform the shuffle
    1301 lib/Target/X86/X86ISelLowering.cpp:    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
    1302 lib/Target/X86/X86ISelLowering.cpp:      ShuffleVec[i] = i * SizeRatio;
    1303 lib/Target/X86/X86ISelLowering.cpp:    // Can't shuffle using an illegal type.
    1304 lib/Target/X86/X86ISelLowering.cpp:    SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
    1305 lib/Target/X86/X86ISelLowering.cpp:                                         &ShuffleVec[0]);
    1306 lib/Target/X86/X86ISelLowering.cpp:  // At least one of the operands should be a vector shuffle.
    1307 lib/Target/X86/X86ISelLowering.cpp:  // If LHS is not a shuffle then pretend it is the shuffle
    1308 lib/Target/X86/X86ISelLowering.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
    1309 lib/Target/X86/X86ISelLowering.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
    1310 lib/Target/X86/X86ISelLowering.cpp:  // Check that the shuffles are both shuffling the same vectors.
    1311 lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(RMask, NumElts);
    1312 lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal adds from adds of shuffles.
    1313 lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal subs from subs of shuffles.
    1314 lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal adds from adds of shuffles.
    1315 lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal adds from adds of shuffles.
    1316 lib/Target/X86/X86ISelLowering.cpp:  case X86ISD::SHUFP:       // Handle all target specific shuffles
    1317 lib/Target/X86/X86ISelLowering.cpp:  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
    1318 lib/Target/X86/X86ISelLowering.h:      /// PSHUFB - Shuffle 16 8-bit values within a vector.
    1319 lib/Target/X86/X86ISelLowering.h:      // Several flavors of instructions with vector shuffle behaviors.
    1320 lib/Target/X86/X86ISelLowering.h:    /// isShuffleMaskLegal - Targets can use this to indicate that they only
    1321 lib/Target/X86/X86ISelLowering.h:    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
    1322 lib/Target/X86/X86ISelLowering.h:    /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
    1323 lib/Target/X86/X86InstrAVX512.td:  // Shuffle with VMOVSS
    1324 lib/Target/X86/X86InstrAVX512.td:  // Shuffle with VMOVSD
    1325 lib/Target/X86/X86InstrAVX512.td:                   EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
    1326 lib/Target/X86/X86InstrAVX512.td:                   EVEX_4V, Sched<[WriteShuffle]>;
    1327 lib/Target/X86/X86InstrFragmentsSIMD.td:// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
    1328 lib/Target/X86/X86InstrInfo.cpp:// FIXME: Some shuffle and unpack instructions have equivalents in different
    1329 lib/Target/X86/X86InstrMMX.td:let Sched = WriteShuffle in {
    1330 lib/Target/X86/X86InstrMMX.td:// -- Shuffle Instructions
    1331 lib/Target/X86/X86InstrMMX.td:                          IIC_MMX_PSHUF>, Sched<[WriteShuffle]>;
    1332 lib/Target/X86/X86InstrMMX.td:                          IIC_MMX_PSHUF>, Sched<[WriteShuffleLd]>;
    1333 lib/Target/X86/X86InstrMMX.td:                       IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;
    1334 lib/Target/X86/X86InstrMMX.td:                      IIC_MMX_PINSRW>, Sched<[WriteShuffle]>;
    1335 lib/Target/X86/X86InstrMMX.td:                     IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>;
    1336 lib/Target/X86/X86InstrMMX.td:let SchedRW = [WriteShuffle] in {
    1337 lib/Target/X86/X86InstrSSE.td:let Sched = WriteShuffle in
    1338 lib/Target/X86/X86InstrSSE.td:let Sched = WriteShuffle in
    1339 lib/Target/X86/X86InstrSSE.td:              IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
    1340 lib/Target/X86/X86InstrSSE.td:                  [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
    1341 lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVSS
    1342 lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVSD
    1343 lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVSS
    1344 lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVSD
    1345 lib/Target/X86/X86InstrSSE.td:           Sched<[WriteFShuffle]>;
    1346 lib/Target/X86/X86InstrSSE.td:    SchedRW = [WriteFShuffle] in {
    1347 lib/Target/X86/X86InstrSSE.td:     Sched<[WriteFShuffleLd, ReadAfterLd]>;
    1348 lib/Target/X86/X86InstrSSE.td:     Sched<[WriteFShuffleLd, ReadAfterLd]>;
    1349 lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVLPS
    1350 lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVLPD
    1351 lib/Target/X86/X86InstrSSE.td:  // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
    1352 lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVLPS
    1353 lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVLPD
    1354 lib/Target/X86/X86InstrSSE.td:                      VEX_4V, Sched<[WriteFShuffle]>;
    1355 lib/Target/X86/X86InstrSSE.td:                      VEX_4V, Sched<[WriteFShuffle]>;
    1356 lib/Target/X86/X86InstrSSE.td:                        IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
    1357 lib/Target/X86/X86InstrSSE.td:                        IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
    1358 lib/Target/X86/X86InstrSSE.td:// SSE 1 & 2 - Shuffle Instructions
    1359 lib/Target/X86/X86InstrSSE.td:/// sse12_shuffle - sse 1 & 2 fp shuffle instructions
    1360 lib/Target/X86/X86InstrSSE.td:multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
    1361 lib/Target/X86/X86InstrSSE.td:            Sched<[WriteFShuffleLd, ReadAfterLd]>;
    1362 lib/Target/X86/X86InstrSSE.td:              Sched<[WriteFShuffle]>;
    1363 lib/Target/X86/X86InstrSSE.td:defm VSHUFPS  : sse12_shuffle<VR128, f128mem, v4f32,
    1364 lib/Target/X86/X86InstrSSE.td:defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
    1365 lib/Target/X86/X86InstrSSE.td:defm VSHUFPD  : sse12_shuffle<VR128, f128mem, v2f64,
    1366 lib/Target/X86/X86InstrSSE.td:defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
    1367 lib/Target/X86/X86InstrSSE.td:  defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
    1368 lib/Target/X86/X86InstrSSE.td:  defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
    1369 lib/Target/X86/X86InstrSSE.td:                           IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
    1370 lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffleLd, ReadAfterLd]>;
    1371 lib/Target/X86/X86InstrSSE.td:// SSE2 - Packed Integer Shuffle Instructions
    1372 lib/Target/X86/X86InstrSSE.td:multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
    1373 lib/Target/X86/X86InstrSSE.td:                      IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
    1374 lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffleLd]>;
    1375 lib/Target/X86/X86InstrSSE.td:                       IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
    1376 lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteShuffleLd]>;
    1377 lib/Target/X86/X86InstrSSE.td:                IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
    1378 lib/Target/X86/X86InstrSSE.td:           Sched<[WriteShuffleLd, ReadAfterLd]>;
    1379 lib/Target/X86/X86InstrSSE.td:defm PSHUFD  : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
    1380 lib/Target/X86/X86InstrSSE.td:defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
    1381 lib/Target/X86/X86InstrSSE.td:defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
    1382 lib/Target/X86/X86InstrSSE.td:      IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
    1383 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffleLd, ReadAfterLd]>;
    1384 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
    1385 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffleLd, ReadAfterLd]>;
    1386 lib/Target/X86/X86InstrSSE.td:       IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
    1387 lib/Target/X86/X86InstrSSE.td:       Sched<[WriteShuffleLd, ReadAfterLd]>;
    1388 lib/Target/X86/X86InstrSSE.td:                Sched<[WriteShuffle]>;
    1389 lib/Target/X86/X86InstrSSE.td:               Sched<[WriteShuffleLd, ReadAfterLd]>;
    1390 lib/Target/X86/X86InstrSSE.td:                      IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
    1391 lib/Target/X86/X86InstrSSE.td:                    [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
    1392 lib/Target/X86/X86InstrSSE.td:                    Sched<[WriteFShuffle]>;
    1393 lib/Target/X86/X86InstrSSE.td:let Sched = WriteShuffle in
    1394 lib/Target/X86/X86InstrSSE.td:      [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
    1395 lib/Target/X86/X86InstrSSE.td:      [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
    1396 lib/Target/X86/X86InstrSSE.td:      []>, Sched<[WriteShuffle]>;
    1397 lib/Target/X86/X86InstrSSE.td:      []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
    1398 lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
    1399 lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
    1400 lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
    1401 lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
    1402 lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
    1403 lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
    1404 lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovsxbd, WriteShuffle>,
    1405 lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovsxwq, WriteShuffle>,
    1406 lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovzxbd, WriteShuffle>,
    1407 lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovzxwq, WriteShuffle>,
    1408 lib/Target/X86/X86InstrSSE.td:                                     WriteShuffle>, VEX;
    1409 lib/Target/X86/X86InstrSSE.td:                                     WriteShuffle>, VEX;
    1410 lib/Target/X86/X86InstrSSE.td:                                       WriteShuffle>, VEX, VEX_L;
    1411 lib/Target/X86/X86InstrSSE.td:                                       WriteShuffle>, VEX, VEX_L;
    1412 lib/Target/X86/X86InstrSSE.td:                                      WriteShuffle>;
    1413 lib/Target/X86/X86InstrSSE.td:                                      WriteShuffle>;
    1414 lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>;
    1415 lib/Target/X86/X86InstrSSE.td:      SchedRW = [WriteShuffleLd, WriteRMW] in
    1416 lib/Target/X86/X86InstrSSE.td:                   []>, Sched<[WriteShuffle]>;
    1417 lib/Target/X86/X86InstrSSE.td:      SchedRW = [WriteShuffleLd, WriteRMW] in
    1418 lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>;
    1419 lib/Target/X86/X86InstrSSE.td:  let SchedRW = [WriteShuffleLd, WriteRMW] in
    1420 lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>, REX_W;
    1421 lib/Target/X86/X86InstrSSE.td:  let SchedRW = [WriteShuffleLd, WriteRMW] in
    1422 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
    1423 lib/Target/X86/X86InstrSSE.td:                   imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
    1424 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
    1425 lib/Target/X86/X86InstrSSE.td:                          imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
    1426 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
    1427 lib/Target/X86/X86InstrSSE.td:                          imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
    1428 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteFShuffle]>;
    1429 lib/Target/X86/X86InstrSSE.td:      Sched<[WriteFShuffleLd, ReadAfterLd]>;
    1430 lib/Target/X86/X86InstrSSE.td:                                        int_x86_avx2_packusdw, WriteShuffle>,
    1431 lib/Target/X86/X86InstrSSE.td:                                      WriteFShuffleLd>, VEX_L;
    1432 lib/Target/X86/X86InstrSSE.td:                                    WriteFShuffleLd>, VEX_L;
    1433 lib/Target/X86/X86InstrSSE.td:                                   WriteFShuffleLd>, VEX_L;
    1434 lib/Target/X86/X86InstrSSE.td:                                           WriteFShuffle>;
    1435 lib/Target/X86/X86InstrSSE.td:                                      WriteFShuffle256>, VEX_L;
    1436 lib/Target/X86/X86InstrSSE.td:                                      WriteFShuffle256>, VEX_L;
    1437 lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
    1438 lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
    1439 lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
    1440 lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffle]>;
    1441 lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffleLd, ReadAfterLd]>;
    1442 lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffle]>;
    1443 lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffleLd]>;
    1444 lib/Target/X86/X86InstrSSE.td:          Sched<[WriteFShuffle]>;
    1445 lib/Target/X86/X86InstrSSE.td:          Sched<[WriteFShuffleLd, ReadAfterLd]>;
    1446 lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>, VEX;
    1447 lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteShuffle256]>, VEX, VEX_L;
    1448 lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteFShuffle256]>, VEX_4V, VEX_L;
    1449 lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteFShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
    1450 lib/Target/X86/X86InstrSSE.td:                     Sched<[WriteShuffle256]>, VEX, VEX_L;
    1451 lib/Target/X86/X86InstrSSE.td:                     Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX, VEX_L;
    1452 lib/Target/X86/X86InstrSSE.td:                            (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
    1453 lib/Target/X86/X86InstrSSE.td:          Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
    1454 lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
    1455 lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
    1456 lib/Target/X86/X86InstrSSE.td:          Sched<[WriteShuffle256]>, VEX, VEX_L;
    1457 lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteFShuffle,  HWPort5,  1>;
    1458 lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteFShuffle256,  HWPort5,  3>;
    1459 lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteShuffle,  HWPort5,  1>;
    1460 lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteShuffle256,  HWPort5,  3>;
    1461 lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteFShuffle,  SBPort5,  1>;
    1462 lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteShuffle,  SBPort15,  1>;
    1463 lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteFShuffle256, SBPort0,  1>;
    1464 lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteShuffle256, SBPort0,  1>;
    1465 lib/Target/X86/X86Schedule.td:defm WriteFShuffle  : X86SchedWritePair; // Floating point vector shuffles.
    1466 lib/Target/X86/X86Schedule.td:defm WriteShuffle  : X86SchedWritePair; // Vector shuffles.
    1467 lib/Target/X86/X86Schedule.td:defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
    1468 lib/Target/X86/X86Schedule.td:defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
    1469 lib/Target/X86/X86ScheduleAtom.td:                      // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
    1470 lib/Target/X86/X86TargetTransformInfo.cpp:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
    1471 lib/Target/X86/X86TargetTransformInfo.cpp:      // lowered into a sequence of shuffles and 2 x pmuludq.
    1472 lib/Target/X86/X86TargetTransformInfo.cpp:  // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
    1473 lib/Target/X86/X86TargetTransformInfo.cpp:  // 2x pmuludq, 2x shuffle.
    1474 lib/Target/X86/X86TargetTransformInfo.cpp:unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
    1475 lib/Target/X86/X86TargetTransformInfo.cpp:  // We only estimate the cost of reverse shuffles.
    1476 lib/Target/X86/X86TargetTransformInfo.cpp:    return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
    1477 lib/Transforms/InstCombine/InstCombine.h:  Instruction *visitShuffleVectorInst(ShuffleVectorInst &SVI);
    1478 lib/Transforms/InstCombine/InstCombineCalls.cpp:    // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
    1479 lib/Transforms/InstCombine/InstCombineCasts.cpp:/// replace it with a shuffle (and vector/vector bitcast) if possible.
    1480 lib/Transforms/InstCombine/InstCombineCasts.cpp:  // Now that the element types match, get the shuffle mask and RHS of the
    1481 lib/Transforms/InstCombine/InstCombineCasts.cpp:  // shuffle to use, which depends on whether we're increasing or decreasing the
    1482 lib/Transforms/InstCombine/InstCombineCasts.cpp:  SmallVector<uint32_t, 16> ShuffleMask;
    1483 lib/Transforms/InstCombine/InstCombineCasts.cpp:    // If we're shrinking the number of elements, just shuffle in the low
    1484 lib/Transforms/InstCombine/InstCombineCasts.cpp:    // elements from the input and use undef as the second shuffle input.
    1485 lib/Transforms/InstCombine/InstCombineCasts.cpp:      ShuffleMask.push_back(i);
    1486 lib/Transforms/InstCombine/InstCombineCasts.cpp:    // If we're increasing the number of elements, shuffle in all of the
    1487 lib/Transforms/InstCombine/InstCombineCasts.cpp:      ShuffleMask.push_back(i);
    1488 lib/Transforms/InstCombine/InstCombineCasts.cpp:      ShuffleMask.push_back(SrcElts);
    1489 lib/Transforms/InstCombine/InstCombineCasts.cpp:  return new ShuffleVectorInst(InVal, V2,
    1490 lib/Transforms/InstCombine/InstCombineCasts.cpp:                                                       ShuffleMask));
    1491 lib/Transforms/InstCombine/InstCombineCasts.cpp:      // the casts with a shuffle and (potentially) a bitcast.
    1492 lib/Transforms/InstCombine/InstCombineCasts.cpp:  if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(Src)) {
    1493 lib/Transforms/InstCombine/InstCombineCasts.cpp:    // Okay, we have (bitcast (shuffle ..)).  Check to see if this is
    1494 lib/Transforms/InstCombine/InstCombineCasts.cpp:      // evaluating the shuffle in the casted destination's type will allow
    1495 lib/Transforms/InstCombine/InstCombineCasts.cpp:        // Return a new shuffle vector.  Use the same element ID's, as we
    1496 lib/Transforms/InstCombine/InstCombineCasts.cpp:        return new ShuffleVectorInst(LHS, RHS, SVI->getOperand(2));
    1497 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:  case Instruction::ShuffleVector: {
    1498 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:    ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
    1499 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:      cast<VectorType>(Shuffle->getOperand(0)->getType())->getNumElements();
    1500 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:        unsigned MaskVal = Shuffle->getMaskValue(i);
    1501 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:                 "shufflevector mask index out of range!");
    1502 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:      unsigned MaskVal = Shuffle->getMaskValue(i);
    1503 lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:                                          Shuffle->getMaskValue(i)));
    1504 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:// ShuffleVector.
    1505 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(V)) {
    1506 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    } else if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(I)) {
    1507 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // If this is extracting an element from a shufflevector, figure out where
    1508 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// CollectSingleShuffleElements - If V is a shuffle of values that ONLY returns
    1509 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// elements from either LHS or RHS, return the shuffle mask and true.
    1510 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:static bool CollectSingleShuffleElements(Value *V, Value *LHS, Value *RHS,
    1511 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:         "Invalid CollectSingleShuffleElements");
    1512 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
    1513 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
    1514 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // TODO: Handle shufflevector here!
    1515 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// CollectShuffleElements - We are building a shuffle of V, using RHS as the
    1516 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// RHS of the shuffle instruction, if it is not null.  Return a shuffle mask
    1517 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// that computes V and the LHS value of the shuffle.
    1518 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:static Value *CollectShuffleElements(Value *V, SmallVectorImpl<Constant*> &Mask,
    1519 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:         "Invalid shuffle!");
    1520 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        // otherwise we'd end up with a shuffle of three inputs.
    1521 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          Value *V = CollectShuffleElements(VecOp, Mask, RHS);
    1522 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          Value *V = CollectShuffleElements(EI->getOperand(0), Mask, RHS);
    1523 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        // vectors, return the vector and the effective shuffle.
    1524 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        if (CollectSingleShuffleElements(IEI, EI->getOperand(0), RHS, Mask))
    1525 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // TODO: Handle shufflevector here!
    1526 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // indexes are constant, try to turn this into a shufflevector operation.
    1527 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // (and any insertelements it points to), into one big shuffle.
    1528 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        Value *LHS = CollectShuffleElements(&IE, Mask, RHS);
    1529 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        // We now have a shuffle of LHS, RHS, Mask.
    1530 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        return new ShuffleVectorInst(LHS, RHS, ConstantVector::get(Mask));
    1531 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// elements were shuffled in a different order.
    1532 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:static bool CanEvaluateShuffled(Value *V, ArrayRef<int> Mask,
    1533 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        if (!CanEvaluateShuffled(I->getOperand(i), Mask, Depth-1))
    1534 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      return CanEvaluateShuffled(I->getOperand(0), Mask, Depth-1);
    1535 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    return ConstantExpr::getShuffleVector(C, UndefValue::get(C->getType()),
    1536 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // by CanEvaluateShuffled.
    1537 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
    1538 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  SmallVector<int, 16> Mask = SVI.getShuffleMask();
    1539 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Undefined shuffle mask -> undefined value.
    1540 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Canonicalize shuffle(x    ,x,mask) -> shuffle(x, undef,mask')
    1541 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Canonicalize shuffle(undef,x,mask) -> shuffle(x, undef,mask').
    1542 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // shuffle(undef,undef,mask) -> undef.
    1543 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    // Analyze the shuffle, are the LHS or RHS and identity shuffles?
    1544 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // Is this an identity shuffle of the LHS value?
    1545 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // Is this an identity shuffle of the RHS value?
    1546 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    // Eliminate identity shuffles.
    1547 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (isa<UndefValue>(RHS) && CanEvaluateShuffled(LHS, Mask)) {
    1548 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // If the LHS is a shufflevector itself, see if we can combine it with this
    1549 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // one without producing an unusual shuffle.
    1550 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x1=shuffle(v1,v2,mask1)
    1551 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,undef,mask)
    1552 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(v1,undef,newMask)
    1553 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x1=shuffle(v1,undef,mask1)
    1554 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,x2,mask)
    1555 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(v1,x2,newMask)
    1556 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x2=shuffle(v2,undef,mask2)
    1557 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,x2,mask)
    1558 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,v2,newMask)
    1559 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x1=shuffle(v1,undef,mask1)
    1560 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x2=shuffle(v2,undef,mask2)
    1561 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,x2,mask)
    1562 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(v1,v2,newMask)
    1563 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // we are absolutely afraid of producing a shuffle mask not in the input
    1564 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // shuffle into two specific shuffles: it may produce worse code.  As such,
    1565 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // we only merge two shuffles if the result is either a splat or one of the
    1566 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // input shuffle masks.  In this case, merging the shuffles just removes
    1567 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  ShuffleVectorInst* LHSShuffle = dyn_cast<ShuffleVectorInst>(LHS);
    1568 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  ShuffleVectorInst* RHSShuffle = dyn_cast<ShuffleVectorInst>(RHS);
    1569 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (LHSShuffle)
    1570 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    if (!isa<UndefValue>(LHSShuffle->getOperand(1)) && !isa<UndefValue>(RHS))
    1571 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      LHSShuffle = NULL;
    1572 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle)
    1573 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    if (!isa<UndefValue>(RHSShuffle->getOperand(1)))
    1574 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      RHSShuffle = NULL;
    1575 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (!LHSShuffle && !RHSShuffle)
    1576 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (LHSShuffle) {
    1577 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    LHSOp0 = LHSShuffle->getOperand(0);
    1578 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    LHSOp1 = LHSShuffle->getOperand(1);
    1579 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle) {
    1580 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    RHSOp0 = RHSShuffle->getOperand(0);
    1581 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (LHSShuffle) {
    1582 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle && RHSOp0Width == LHSWidth) {
    1583 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    LHSMask = LHSShuffle->getShuffleMask();
    1584 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle && newRHS != RHS)
    1585 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    RHSMask = RHSShuffle->getShuffleMask();
    1586 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Create a new mask for the new ShuffleVectorInst so that the new
    1587 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // ShuffleVectorInst is equivalent to the original one.
    1588 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          assert(isa<UndefValue>(RHSShuffle->getOperand(1))
    1589 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // If the result mask is equal to one of the original shuffle masks,
    1590 lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    return new ShuffleVectorInst(newLHS, newRHS, ConstantVector::get(Elts));
    1591 lib/Transforms/Instrumentation/DataFlowSanitizer.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &I);
    1592 lib/Transforms/Instrumentation/DataFlowSanitizer.cpp:void DFSanVisitor::visitShuffleVectorInst(ShuffleVectorInst &I) {
    1593 lib/Transforms/Instrumentation/MemorySanitizer.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &I) {
    1594 lib/Transforms/Instrumentation/MemorySanitizer.cpp:    setShadow(&I, IRB.CreateShuffleVector(getShadow(&I, 0), getShadow(&I, 1),
    1595 lib/Transforms/ObjCARC/ObjCARCUtil.cpp:    case Instruction::ShuffleVector:
    1596 lib/Transforms/Scalar/EarlyCSE.cpp:             isa<InsertElementInst>(Inst) || isa<ShuffleVectorInst>(Inst) ||
    1597 lib/Transforms/Scalar/EarlyCSE.cpp:          isa<ShuffleVectorInst>(Inst)) && "Invalid/unknown instruction");
    1598 lib/Transforms/Scalar/GVN.cpp:    case Instruction::ShuffleVector:
    1599 lib/Transforms/Scalar/LICM.cpp:      !isa<ShuffleVectorInst>(I) && !isa<ExtractValueInst>(I) &&
    1600 lib/Transforms/Scalar/SCCP.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &I);
    1601 lib/Transforms/Scalar/SCCP.cpp:void SCCPSolver::visitShuffleVectorInst(ShuffleVectorInst &I) {
    1602 lib/Transforms/Scalar/SCCP.cpp:    markConstant(&I, ConstantExpr::getShuffleVector(V1, V2, Mask));
    1603 lib/Transforms/Scalar/SROA.cpp:static cl::opt<bool> SROARandomShuffleSlices("sroa-random-shuffle-slices",
    1604 lib/Transforms/Scalar/SROA.cpp:  if (SROARandomShuffleSlices) {
    1605 lib/Transforms/Scalar/SROA.cpp:    std::shuffle(Slices.begin(), Slices.end(), MT);
    1606 lib/Transforms/Scalar/SROA.cpp:  V = IRB.CreateShuffleVector(V, UndefValue::get(V->getType()),
    1607 lib/Transforms/Scalar/SROA.cpp:  DEBUG(dbgs() << "     shuffle: " << *V << "\n");
    1608 lib/Transforms/Scalar/SROA.cpp:  // use a shuffle vector to widen it with undef elements, and then
    1609 lib/Transforms/Scalar/SROA.cpp:  // a second shuffle vector to select between the loaded vector and the
    1610 lib/Transforms/Scalar/SROA.cpp:  V = IRB.CreateShuffleVector(V, UndefValue::get(V->getType()),
    1611 lib/Transforms/Scalar/SROA.cpp:  DEBUG(dbgs() << "    shuffle: " << *V << "\n");
    1612 lib/Transforms/Scalar/Scalarizer.cpp:  bool visitShuffleVectorInst(ShuffleVectorInst &);
    1613 lib/Transforms/Scalar/Scalarizer.cpp:bool Scalarizer::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
    1614 lib/Transforms/Vectorize/BBVectorize.cpp:    void fillNewShuffleMask(LLVMContext& Context, Instruction *J,
    1615 lib/Transforms/Vectorize/BBVectorize.cpp:    Value *getReplacementShuffleMask(LLVMContext& Context, Instruction *I,
    1616 lib/Transforms/Vectorize/BBVectorize.cpp:      } else if (ShuffleVectorInst *SI = dyn_cast<ShuffleVectorInst>(I)) {
    1617 lib/Transforms/Vectorize/BBVectorize.cpp:      case Instruction::ShuffleVector:
    1618 lib/Transforms/Vectorize/BBVectorize.cpp:    } else if (!(I->isBinaryOp() || isa<ShuffleVectorInst>(I) ||
    1619 lib/Transforms/Vectorize/BBVectorize.cpp:      // instructions (because combining these often results in a shuffle),
    1620 lib/Transforms/Vectorize/BBVectorize.cpp:        // shuffle chains.
    1621 lib/Transforms/Vectorize/BBVectorize.cpp:          if (!isa<ShuffleVectorInst>(S->first) &&
    1622 lib/Transforms/Vectorize/BBVectorize.cpp:          // the cost of shuffles.
    1623 lib/Transforms/Vectorize/BBVectorize.cpp:                int ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
    1624 lib/Transforms/Vectorize/BBVectorize.cpp:                    ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
    1625 lib/Transforms/Vectorize/BBVectorize.cpp:                    ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
    1626 lib/Transforms/Vectorize/BBVectorize.cpp:          // to shuffles, inserts or extracts can be merged, and so contribute
    1627 lib/Transforms/Vectorize/BBVectorize.cpp:              if (ShuffleVectorInst *SI = dyn_cast<ShuffleVectorInst>(*I)) {
    1628 lib/Transforms/Vectorize/BBVectorize.cpp:                // Shuffle can be folded if it has no other input
    1629 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
    1630 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
    1631 lib/Transforms/Vectorize/BBVectorize.cpp:              if (ShuffleVectorInst *SI = dyn_cast<ShuffleVectorInst>(*I)) {
    1632 lib/Transforms/Vectorize/BBVectorize.cpp:                // Shuffle can be folded if it has no other input
    1633 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
    1634 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
    1635 lib/Transforms/Vectorize/BBVectorize.cpp:                // type, then they can be replaced with a shuffle
    1636 lib/Transforms/Vectorize/BBVectorize.cpp:                // If both are a shuffle with equal operand types and only two
    1637 lib/Transforms/Vectorize/BBVectorize.cpp:                // shuffle
    1638 lib/Transforms/Vectorize/BBVectorize.cpp:                ShuffleVectorInst *SIO1 = dyn_cast<ShuffleVectorInst>(O1),
    1639 lib/Transforms/Vectorize/BBVectorize.cpp:                                  *SIO2 = dyn_cast<ShuffleVectorInst>(O2);
    1640 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
    1641 lib/Transforms/Vectorize/BBVectorize.cpp:                  ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
    1642 lib/Transforms/Vectorize/BBVectorize.cpp:                // both need to be shuffled together.
    1643 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib += (int) getInstrCost(Instruction::ShuffleVector,
    1644 lib/Transforms/Vectorize/BBVectorize.cpp:                // both need to be shuffled together.
    1645 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib += (int) getInstrCost(Instruction::ShuffleVector,
    1646 lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
    1647 lib/Transforms/Vectorize/BBVectorize.cpp:                  ESContrib += (int) getInstrCost(Instruction::ShuffleVector,
    1648 lib/Transforms/Vectorize/BBVectorize.cpp:  void BBVectorize::fillNewShuffleMask(LLVMContext& Context, Instruction *J,
    1649 lib/Transforms/Vectorize/BBVectorize.cpp:      int m = cast<ShuffleVectorInst>(J)->getMaskValue(v);
    1650 lib/Transforms/Vectorize/BBVectorize.cpp:  // Returns the value that is to be used as the vector-shuffle mask to the
    1651 lib/Transforms/Vectorize/BBVectorize.cpp:  Value *BBVectorize::getReplacementShuffleMask(LLVMContext& Context,
    1652 lib/Transforms/Vectorize/BBVectorize.cpp:    // This is the shuffle mask. We need to append the second
    1653 lib/Transforms/Vectorize/BBVectorize.cpp:    fillNewShuffleMask(Context, I, 0,        NumInElemJ, NumInElemI,
    1654 lib/Transforms/Vectorize/BBVectorize.cpp:    fillNewShuffleMask(Context, J, NumElemI, NumInElemI, NumInElemJ,
    1655 lib/Transforms/Vectorize/BBVectorize.cpp:    // exist). We might need a shuffle.
    1656 lib/Transforms/Vectorize/BBVectorize.cpp:    ShuffleVectorInst *LSV = dyn_cast<ShuffleVectorInst>(LOp);
    1657 lib/Transforms/Vectorize/BBVectorize.cpp:    ShuffleVectorInst *HSV = dyn_cast<ShuffleVectorInst>(HOp);
    1658 lib/Transforms/Vectorize/BBVectorize.cpp:    // FIXME: If we're fusing shuffle instructions, then we can't apply this
    1659 lib/Transforms/Vectorize/BBVectorize.cpp:    // optimization. The input vectors to the shuffle might be a different
    1660 lib/Transforms/Vectorize/BBVectorize.cpp:    // length from the shuffle outputs. Unfortunately, the replacement
    1661 lib/Transforms/Vectorize/BBVectorize.cpp:    // shuffle mask has already been formed, and the mask entries are sensitive
    1662 lib/Transforms/Vectorize/BBVectorize.cpp:    bool IsSizeChangeShuffle =
    1663 lib/Transforms/Vectorize/BBVectorize.cpp:      isa<ShuffleVectorInst>(L) &&
    1664 lib/Transforms/Vectorize/BBVectorize.cpp:    if ((LEE || LSV) && (HEE || HSV) && !IsSizeChangeShuffle) {
    1665 lib/Transforms/Vectorize/BBVectorize.cpp:          // A shuffle is needed.
    1666 lib/Transforms/Vectorize/BBVectorize.cpp:            new ShuffleVectorInst(I1, UndefValue::get(I1T),
    1667 lib/Transforms/Vectorize/BBVectorize.cpp:        // smaller one will need to grow before they can be shuffled together.
    1668 lib/Transforms/Vectorize/BBVectorize.cpp:            new ShuffleVectorInst(I1, UndefValue::get(I1T),
    1669 lib/Transforms/Vectorize/BBVectorize.cpp:            new ShuffleVectorInst(I2, UndefValue::get(I2T),
    1670 lib/Transforms/Vectorize/BBVectorize.cpp:        // Now that both I1 and I2 are the same length we can shuffle them
    1671 lib/Transforms/Vectorize/BBVectorize.cpp:          new ShuffleVectorInst(I1, I2, ConstantVector::get(Mask),
    1672 lib/Transforms/Vectorize/BBVectorize.cpp:        // The two vector inputs to the shuffle must be the same length,
    1673 lib/Transforms/Vectorize/BBVectorize.cpp:          NLOp = new ShuffleVectorInst(LOp, UndefValue::get(ArgTypeL),
    1674 lib/Transforms/Vectorize/BBVectorize.cpp:          NHOp = new ShuffleVectorInst(HOp, UndefValue::get(ArgTypeH),
    1675 lib/Transforms/Vectorize/BBVectorize.cpp:      Instruction *BV = new ShuffleVectorInst(LOp, HOp,
    1676 lib/Transforms/Vectorize/BBVectorize.cpp:      } else if (isa<ShuffleVectorInst>(I) && o == NumOperands-1) {
    1677 lib/Transforms/Vectorize/BBVectorize.cpp:        ReplacedOperands[o] = getReplacementShuffleMask(Context, I, J);
    1678 lib/Transforms/Vectorize/BBVectorize.cpp:  // original I and J instructions. These are generally vector shuffles
    1679 lib/Transforms/Vectorize/BBVectorize.cpp:        K1 = new ShuffleVectorInst(K, UndefValue::get(VType),
    1680 lib/Transforms/Vectorize/BBVectorize.cpp:        K2 = new ShuffleVectorInst(K, UndefValue::get(VType),
    1681 lib/Transforms/Vectorize/BBVectorize.cpp:        // flip it if that will yield fewer shuffles. We count the number
    1682 lib/Transforms/Vectorize/LoopVectorize.cpp:  /// instruction (shuffle) for loop invariant values and for the induction
    1683 lib/Transforms/Vectorize/LoopVectorize.cpp:  /// Generate a shuffle sequence that will reverse the vector Vec.
    1684 lib/Transforms/Vectorize/LoopVectorize.cpp:  SmallVector<Constant*, 8> ShuffleMask;
    1685 lib/Transforms/Vectorize/LoopVectorize.cpp:    ShuffleMask.push_back(Builder.getInt32(VF - i - 1));
    1686 lib/Transforms/Vectorize/LoopVectorize.cpp:  return Builder.CreateShuffleVector(Vec, UndefValue::get(Vec->getType()),
    1687 lib/Transforms/Vectorize/LoopVectorize.cpp:                                     ConstantVector::get(ShuffleMask),
    1688 lib/Transforms/Vectorize/LoopVectorize.cpp:           isa<ShuffleVectorInst>(I) || isa<GetElementPtrInst>(I);
    1689 lib/Transforms/Vectorize/LoopVectorize.cpp:      // VF is a power of 2 so we can emit the reduction using log2(VF) shuffles
    1690 lib/Transforms/Vectorize/LoopVectorize.cpp:      SmallVector<Constant*, 32> ShuffleMask(VF, 0);
    1691 lib/Transforms/Vectorize/LoopVectorize.cpp:          ShuffleMask[j] = Builder.getInt32(i/2 + j);
    1692 lib/Transforms/Vectorize/LoopVectorize.cpp:        std::fill(&ShuffleMask[i/2], ShuffleMask.end(),
    1693 lib/Transforms/Vectorize/LoopVectorize.cpp:        Builder.CreateShuffleVector(TmpVec,
    1694 lib/Transforms/Vectorize/LoopVectorize.cpp:                                    ConstantVector::get(ShuffleMask),
    1695 lib/Transforms/Vectorize/LoopVectorize.cpp:      Cost += TTI.getShuffleCost(TargetTransformInfo::SK_Reverse,
    1696 lib/Transforms/Vectorize/SLPVectorizer.cpp:      return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy, 0);
    1697 lib/Transforms/Vectorize/SLPVectorizer.cpp:/// \brief Generate a shuffle mask to be used in a reduction tree.
    1698 lib/Transforms/Vectorize/SLPVectorizer.cpp:static Value *createRdxShuffleMask(unsigned VecLen, unsigned NumEltsToRdx,
    1699 lib/Transforms/Vectorize/SLPVectorizer.cpp:  SmallVector<Constant *, 32> ShuffleMask(
    1700 lib/Transforms/Vectorize/SLPVectorizer.cpp:      ShuffleMask[i] = Builder.getInt32(2 * i + !IsLeft);
    1701 lib/Transforms/Vectorize/SLPVectorizer.cpp:      ShuffleMask[i] = Builder.getInt32(NumEltsToRdx + i);
    1702 lib/Transforms/Vectorize/SLPVectorizer.cpp:  return ConstantVector::get(ShuffleMask);
    1703 lib/Transforms/Vectorize/SLPVectorizer.cpp:          createRdxShuffleMask(ReduxWidth, i, true, true, Builder);
    1704 lib/Transforms/Vectorize/SLPVectorizer.cpp:          createRdxShuffleMask(ReduxWidth, i, true, false, Builder);
    1705 lib/Transforms/Vectorize/SLPVectorizer.cpp:        Value *LeftShuf = Builder.CreateShuffleVector(
    1706 lib/Transforms/Vectorize/SLPVectorizer.cpp:        Value *RightShuf = Builder.CreateShuffleVector(
    1707 lib/Transforms/Vectorize/SLPVectorizer.cpp:          createRdxShuffleMask(ReduxWidth, i, false, false, Builder);
    1708 lib/Transforms/Vectorize/SLPVectorizer.cpp:        Value *Shuf = Builder.CreateShuffleVector(
    1709 Robs-MacBook-Pro:llvm cameron$
    1710 lib/Target/X86/Utils/X86ShuffleDecode.cpp://===-- X86ShuffleDecode.cpp - X86 shuffle decode logic -------------------===//
    1711 lib/Target/X86/Utils/X86ShuffleDecode.cpp:// Define several functions to decode x86 specific shuffle semantics into a
    1712 lib/Target/X86/Utils/X86ShuffleDecode.cpp:#include "X86ShuffleDecode.h"
    1713 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
    1714 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(0);
    1715 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(1);
    1716 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(2);
    1717 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(3);
    1718 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask[CountD] = InVal;
    1719 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero;
    1720 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero;
    1721 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero;
    1722 lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero;
    1723 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask) {
    1724 lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(NElts+i);
    1725 lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(i);
    1726 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask) {
    1727 lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(i);
    1728 lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(NElts+i);
    1729 lib/Target/X86/Utils/X86ShuffleDecode.cpp:                       SmallVectorImpl<int> &ShuffleMask) {
    1730 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(Base + l);
    1731 lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodePSHUFMask - This decodes the shuffle masks for pshufd, and vpermilp*.
    1732 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
    1733 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(NewImm % NumLaneElts + l);
    1734 lib/Target/X86/Utils/X86ShuffleDecode.cpp:                       SmallVectorImpl<int> &ShuffleMask) {
    1735 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + i);
    1736 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + 4 + (NewImm & 3));
    1737 lib/Target/X86/Utils/X86ShuffleDecode.cpp:                       SmallVectorImpl<int> &ShuffleMask) {
    1738 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + (NewImm & 3));
    1739 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + i);
    1740 lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
    1741 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
    1742 lib/Target/X86/Utils/X86ShuffleDecode.cpp:        ShuffleMask.push_back(NewImm % NumLaneElts + s + l);
    1743 lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeUNPCKHMask - This decodes the shuffle masks for unpckhps/unpckhpd
    1744 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) {
    1745 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i);          // Reads from dest/src1
    1746 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i+NumElts);  // Reads from src/src2
    1747 lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeUNPCKLMask - This decodes the shuffle masks for unpcklps/unpcklpd
    1748 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) {
    1749 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i);          // Reads from dest/src1
    1750 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i+NumElts);  // Reads from src/src2
    1751 lib/Target/X86/Utils/X86ShuffleDecode.cpp:                          SmallVectorImpl<int> &ShuffleMask) {
    1752 lib/Target/X86/Utils/X86ShuffleDecode.cpp:    return; // Not a shuffle
    1753 lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i);
    1754 lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeVPERMMask - this decodes the shuffle masks for VPERMQ/VPERMPD.
    1755 lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
    1756 lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back((Imm >> (2*i)) & 3);
    1757 lib/Target/X86/Utils/X86ShuffleDecode.h://===-- X86ShuffleDecode.h - X86 shuffle decode logic -----------*-C++-*---===//
    1758 lib/Target/X86/Utils/X86ShuffleDecode.h:// Define several functions to decode x86 specific shuffle semantics into a
    1759 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
    1760 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
    1761 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
    1762 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
    1763 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
    1764 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
    1765 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
    1766 lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
    1767 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
    1768 lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeUNPCKHMask - This decodes the shuffle masks for unpckhps/unpckhpd
    1769 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
    1770 lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeUNPCKLMask - This decodes the shuffle masks for unpcklps/unpcklpd
    1771 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
    1772 lib/Target/X86/Utils/X86ShuffleDecode.h:                          SmallVectorImpl<int> &ShuffleMask);
    1773 lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeVPERMMask - this decodes the shuffle masks for VPERMQ/VPERMPD.
    1774 lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
    1775 
    1776 }}}