8 | | ~~shufflevector <8 x i8> %v1, <8 x i8> %v2~~, |

9 | | <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ; yields <8 x i8> |

| 8 | %v3 = shufflevector <8 x i8> %v1, <8 x i8> undef, |

| 9 | <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ; yields <8 x i8> |

| 16 | |

| 17 | Generalizing this pattern, we may have arbitrary rotations expressed using shuffle masks. |

| 18 | For example, consider the shufflevector of 4-bit fields: |

| 19 | {{{ |

| 20 | %v3 = shufflevector <8 x i4> %v1, <8 x i4> undef, |

| 21 | <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4> ; yields <8 x i8> |

| 22 | }}} |

| 23 | Shuffles on 4-bit fields are generally not supported by SIMD instruction sets, but this one |

| 24 | can be implemented by transforming to 16-bit vector shift operations. |

| 25 | {{{ |

| 26 | %t0 = bitcast %v1 to <2 x i16> |

| 27 | %t1 = shl %t0, <2 x i16> <i16 12, i16 12> |

| 28 | %t2 = lshr4 %t0, <2 x i16> <i16 4, i16 4> |

| 29 | %v3 = xor %t1, %t2 |

| 30 | }}} |

| 31 | |

| 32 | Can these examples be turned into general rules that systematically capture |

| 33 | these special cases? |

| 34 | |

| 35 | == Vectorized Sequential Code == |

| 36 | |

| 37 | If there is no known fully parallel implementation of a particular case, it may |

| 38 | still be possible to partially parallelize by making a vectorized sequential |

| 39 | loop. |

23 | | <128 x i1> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, ...> ~~ ; yields <8 x i8>~~ |

| 50 | <128 x i1> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, ...> |