Changes between Version 7 and Version 8 of ShuffleVector


Ignore:
Timestamp:
Apr 16, 2014, 2:31:26 AM (3 years ago)
Author:
cameron
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • ShuffleVector

    v7 v8  
    4242See the BitShuffle subproject.
    4343
     44== LLVM Source Code and Shuffles ==
     45
     46The following grep results show shuffle occurring throughout the LLVM code base in all kinds of special cases.
     47{{{
     48include/llvm-c/Core.h:  LLVMShuffleVector  = 52,
     49include/llvm-c/Core.h:      macro(ShuffleVectorInst)              \
     50include/llvm-c/Core.h:LLVMValueRef LLVMConstShuffleVector(LLVMValueRef VectorAConstant,
     51include/llvm-c/Core.h:LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef, LLVMValueRef V1,
     52lib/Analysis/ConstantFolding.cpp:  case Instruction::ShuffleVector:
     53lib/Analysis/ConstantFolding.cpp:    return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]);
     54lib/Analysis/CostModel.cpp:static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
     55lib/Analysis/CostModel.cpp:  // We don't need a shuffle if we just want to have element 0 in position 0 of
     56lib/Analysis/CostModel.cpp:  SmallVector<int, 16> ActualMask = SI->getShuffleMask();
     57lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
     58lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
     59lib/Analysis/CostModel.cpp:  ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(L);
     60lib/Analysis/CostModel.cpp:  ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(R);
     61lib/Analysis/CostModel.cpp:  // On level 0 we can omit one shufflevector instruction.
     62lib/Analysis/CostModel.cpp:  // Shuffle inputs must match.
     63lib/Analysis/CostModel.cpp:    // If we have two shuffles their operands must match.
     64lib/Analysis/CostModel.cpp:    // On the first level we can omit the shufflevector <0, undef,...>. So the
     65lib/Analysis/CostModel.cpp:    // input to the other shufflevector <1, undef> must match with one of the
     66lib/Analysis/CostModel.cpp:    //  %NextLevelOpL = shufflevector %R, <1, undef ...>
     67lib/Analysis/CostModel.cpp:  // Shuffle mask for pairwise operation must match.
     68lib/Analysis/CostModel.cpp:  if (matchPairwiseShuffleMask(LS, true, Level)) {
     69lib/Analysis/CostModel.cpp:    if (!matchPairwiseShuffleMask(RS, false, Level))
     70lib/Analysis/CostModel.cpp:  } else if (matchPairwiseShuffleMask(RS, true, Level)) {
     71lib/Analysis/CostModel.cpp:    if (!matchPairwiseShuffleMask(LS, false, Level))
     72lib/Analysis/CostModel.cpp:  // We look for a sequence of shuffle,shuffle,add triples like the following
     73lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
     74lib/Analysis/CostModel.cpp:  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
     75lib/Analysis/CostModel.cpp:  // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
     76lib/Analysis/CostModel.cpp:  // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
     77lib/Analysis/CostModel.cpp:static std::pair<Value *, ShuffleVectorInst *>
     78lib/Analysis/CostModel.cpp:getShuffleAndOtherOprd(BinaryOperator *B) {
     79lib/Analysis/CostModel.cpp:  ShuffleVectorInst *S = 0;
     80lib/Analysis/CostModel.cpp:  if ((S = dyn_cast<ShuffleVectorInst>(L)))
     81lib/Analysis/CostModel.cpp:  S = dyn_cast<ShuffleVectorInst>(R);
     82lib/Analysis/CostModel.cpp:  // We look for a sequence of shuffles and adds like the following matching one
     83lib/Analysis/CostModel.cpp:  // fadd, shuffle vector pair at a time.
     84lib/Analysis/CostModel.cpp:  // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
     85lib/Analysis/CostModel.cpp:  // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
     86lib/Analysis/CostModel.cpp:  SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
     87lib/Analysis/CostModel.cpp:    ShuffleVectorInst *Shuffle;
     88lib/Analysis/CostModel.cpp:    std::tie(NextRdxOp, Shuffle) = getShuffleAndOtherOprd(BinOp);
     89lib/Analysis/CostModel.cpp:    // Check the current reduction operation and the shuffle use the same value.
     90lib/Analysis/CostModel.cpp:    if (Shuffle == 0)
     91lib/Analysis/CostModel.cpp:    if (Shuffle->getOperand(0) != NextRdxOp)
     92lib/Analysis/CostModel.cpp:    // Check that shuffle masks matches.
     93lib/Analysis/CostModel.cpp:      ShuffleMask[j] = MaskStart + j;
     94lib/Analysis/CostModel.cpp:    std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
     95lib/Analysis/CostModel.cpp:    SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
     96lib/Analysis/CostModel.cpp:    if (!matchMask(ShuffleMask, Mask))
     97lib/Analysis/CostModel.cpp:    // Try to match a reduction sequence (series of shufflevector and vector
     98lib/Analysis/CostModel.cpp:  case Instruction::ShuffleVector: {
     99lib/Analysis/CostModel.cpp:    const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
     100lib/Analysis/CostModel.cpp:    Type *VecTypOp0 = Shuffle->getOperand(0)->getType();
     101lib/Analysis/CostModel.cpp:    SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
     102lib/Analysis/CostModel.cpp:      return TTI->getShuffleCost(TargetTransformInfo::SK_Reverse, VecTypOp0, 0,
     103lib/Analysis/Lint.cpp:  // TODO: Look through vector insert/extract/shuffle.
     104lib/Analysis/TargetTransformInfo.cpp:unsigned TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Tp,
     105lib/Analysis/TargetTransformInfo.cpp:  return PrevTTI->getShuffleCost(Kind, Tp, Index, SubTp);
     106lib/Analysis/TargetTransformInfo.cpp:  unsigned getShuffleCost(ShuffleKind Kind, Type *Ty,
     107lib/AsmParser/LLLexer.cpp:  INSTKEYWORD(shufflevector,  ShuffleVector);
     108lib/AsmParser/LLParser.cpp:  case lltok::kw_shufflevector:
     109lib/AsmParser/LLParser.cpp:    } else if (Opc == Instruction::ShuffleVector) {
     110lib/AsmParser/LLParser.cpp:        return Error(ID.Loc, "expected three operands to shufflevector");
     111lib/AsmParser/LLParser.cpp:      if (!ShuffleVectorInst::isValidOperands(Elts[0], Elts[1], Elts[2]))
     112lib/AsmParser/LLParser.cpp:        return Error(ID.Loc, "invalid operands to shufflevector");
     113lib/AsmParser/LLParser.cpp:                 ConstantExpr::getShuffleVector(Elts[0], Elts[1],Elts[2]);
     114lib/AsmParser/LLParser.cpp:  case lltok::kw_shufflevector:  return ParseShuffleVector(Inst, PFS);
     115lib/AsmParser/LLParser.cpp:/// ParseShuffleVector
     116lib/AsmParser/LLParser.cpp:///   ::= 'shufflevector' TypeAndValue ',' TypeAndValue ',' TypeAndValue
     117lib/AsmParser/LLParser.cpp:bool LLParser::ParseShuffleVector(Instruction *&Inst, PerFunctionState &PFS) {
     118lib/AsmParser/LLParser.cpp:      ParseToken(lltok::comma, "expected ',' after shuffle mask") ||
     119lib/AsmParser/LLParser.cpp:      ParseToken(lltok::comma, "expected ',' after shuffle value") ||
     120lib/AsmParser/LLParser.cpp:  if (!ShuffleVectorInst::isValidOperands(Op0, Op1, Op2))
     121lib/AsmParser/LLParser.cpp:    return Error(Loc, "invalid shufflevector operands");
     122lib/AsmParser/LLParser.cpp:  Inst = new ShuffleVectorInst(Op0, Op1, Op2);
     123lib/AsmParser/LLParser.h:    bool ParseShuffleVector(Instruction *&I, PerFunctionState &PFS);
     124lib/AsmParser/LLToken.h:    kw_extractelement, kw_insertelement, kw_shufflevector,
     125lib/CodeGen/BasicTargetTransformInfo.cpp:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
     126lib/CodeGen/BasicTargetTransformInfo.cpp:unsigned BasicTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
     127lib/CodeGen/BasicTargetTransformInfo.cpp:  // Assume the pairwise shuffles add a cost.
     128lib/CodeGen/BasicTargetTransformInfo.cpp:  unsigned ShuffleCost =
     129lib/CodeGen/BasicTargetTransformInfo.cpp:      TopTTI->getShuffleCost(SK_ExtractSubvector, Ty, NumVecElts / 2, Ty);
     130lib/CodeGen/BasicTargetTransformInfo.cpp:  return ShuffleCost + ArithCost + getScalarizationOverhead(Ty, false, true);
     131lib/CodeGen/CodeGenPrepare.cpp:    bool OptimizeShuffleVectorInst(ShuffleVectorInst *SI);
     132lib/CodeGen/CodeGenPrepare.cpp:static bool isBroadcastShuffle(ShuffleVectorInst *SVI) {
     133lib/CodeGen/CodeGenPrepare.cpp:  SmallVector<int, 16> Mask(SVI->getShuffleMask());
     134lib/CodeGen/CodeGenPrepare.cpp:/// it's often worth sinking a shufflevector splat down to its use so that
     135lib/CodeGen/CodeGenPrepare.cpp:bool CodeGenPrepare::OptimizeShuffleVectorInst(ShuffleVectorInst *SVI) {
     136lib/CodeGen/CodeGenPrepare.cpp:  // We only expect better codegen by sinking a shuffle if we can recognise a
     137lib/CodeGen/CodeGenPrepare.cpp:  if (!isBroadcastShuffle(SVI))
     138lib/CodeGen/CodeGenPrepare.cpp:  // InsertedShuffles - Only insert a shuffle in each block once.
     139lib/CodeGen/CodeGenPrepare.cpp:  DenseMap<BasicBlock*, Instruction*> InsertedShuffles;
     140lib/CodeGen/CodeGenPrepare.cpp:    // Everything checks out, sink the shuffle if the user's block doesn't
     141lib/CodeGen/CodeGenPrepare.cpp:    Instruction *&InsertedShuffle = InsertedShuffles[UserBB];
     142lib/CodeGen/CodeGenPrepare.cpp:    if (!InsertedShuffle) {
     143lib/CodeGen/CodeGenPrepare.cpp:      InsertedShuffle = new ShuffleVectorInst(SVI->getOperand(0),
     144lib/CodeGen/CodeGenPrepare.cpp:    User->replaceUsesOfWith(SVI, InsertedShuffle);
     145lib/CodeGen/CodeGenPrepare.cpp:  // If we removed all uses, nuke the shuffle.
     146lib/CodeGen/CodeGenPrepare.cpp:  if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(I))
     147lib/CodeGen/CodeGenPrepare.cpp:    return OptimizeShuffleVectorInst(SVI);
     148lib/CodeGen/MachineScheduler.cpp:// Machine Instruction Shuffler for Correctness Testing
     149lib/CodeGen/MachineScheduler.cpp:class InstructionShuffler : public MachineSchedStrategy {
     150lib/CodeGen/MachineScheduler.cpp:  InstructionShuffler(bool alternate, bool topdown)
     151lib/CodeGen/MachineScheduler.cpp:static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
     152lib/CodeGen/MachineScheduler.cpp:  return new ScheduleDAGMILive(C, new InstructionShuffler(Alternate, TopDown));
     153lib/CodeGen/MachineScheduler.cpp:static MachineSchedRegistry ShufflerRegistry(
     154lib/CodeGen/MachineScheduler.cpp:  "shuffle", "Shuffle machine instructions alternating directions",
     155lib/CodeGen/MachineScheduler.cpp:  createInstructionShuffler);
     156lib/CodeGen/TargetLoweringBase.cpp:  case ShuffleVector:  return ISD::VECTOR_SHUFFLE;
     157lib/IR/AsmWriter.cpp:    // Select, Store and ShuffleVector always print all types.
     158lib/IR/AsmWriter.cpp:    if (isa<SelectInst>(I) || isa<StoreInst>(I) || isa<ShuffleVectorInst>(I)
     159lib/IR/AutoUpgrade.cpp:        Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
     160lib/IR/ConstantFold.cpp:Constant *llvm::ConstantFoldShuffleVectorInstruction(Constant *V1,
     161lib/IR/ConstantFold.cpp:  // Undefined shuffle mask -> undefined value.
     162lib/IR/ConstantFold.cpp:  // Loop over the shuffle mask, evaluating each element.
     163lib/IR/ConstantFold.cpp:    int Elt = ShuffleVectorInst::getMaskValue(Mask, i);
     164lib/IR/ConstantFold.h:  Constant *ConstantFoldShuffleVectorInstruction(Constant *V1, Constant *V2,
     165lib/IR/Constants.cpp:  case Instruction::ShuffleVector:
     166lib/IR/Constants.cpp:    return ConstantExpr::getShuffleVector(Ops[0], Ops[1], Ops[2]);
     167lib/IR/Constants.cpp:Constant *ConstantExpr::getShuffleVector(Constant *V1, Constant *V2,
     168lib/IR/Constants.cpp:  assert(ShuffleVectorInst::isValidOperands(V1, V2, Mask) &&
     169lib/IR/Constants.cpp:         "Invalid shuffle vector constant expr operands!");
     170lib/IR/Constants.cpp:  if (Constant *FC = ConstantFoldShuffleVectorInstruction(V1, V2, Mask))
     171lib/IR/Constants.cpp:  const ExprMapKeyType Key(Instruction::ShuffleVector, ArgVec);
     172lib/IR/Constants.cpp:  case Instruction::ShuffleVector:
     173lib/IR/Constants.cpp:    return new ShuffleVectorInst(Ops[0], Ops[1], Ops[2]);
     174lib/IR/ConstantsContext.h:/// ShuffleVectorConstantExpr - This class is private to
     175lib/IR/ConstantsContext.h:/// shufflevector constant exprs.
     176lib/IR/ConstantsContext.h:class ShuffleVectorConstantExpr : public ConstantExpr {
     177lib/IR/ConstantsContext.h:  ShuffleVectorConstantExpr(Constant *C1, Constant *C2, Constant *C3)
     178lib/IR/ConstantsContext.h:                 Instruction::ShuffleVector,
     179lib/IR/ConstantsContext.h:struct OperandTraits<ShuffleVectorConstantExpr> :
     180lib/IR/ConstantsContext.h:    public FixedNumOperandTraits<ShuffleVectorConstantExpr, 3> {
     181lib/IR/ConstantsContext.h:DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorConstantExpr, Value)
     182lib/IR/ConstantsContext.h:    if (V.opcode == Instruction::ShuffleVector)
     183lib/IR/ConstantsContext.h:      return new ShuffleVectorConstantExpr(V.operands[0], V.operands[1],
     184lib/IR/Core.cpp:LLVMValueRef LLVMConstShuffleVector(LLVMValueRef VectorAConstant,
     185lib/IR/Core.cpp:  return wrap(ConstantExpr::getShuffleVector(unwrap<Constant>(VectorAConstant),
     186lib/IR/Core.cpp:LLVMValueRef LLVMBuildShuffleVector(LLVMBuilderRef B, LLVMValueRef V1,
     187lib/IR/Core.cpp:  return wrap(unwrap(B)->CreateShuffleVector(unwrap(V1), unwrap(V2),
     188lib/IR/Instruction.cpp:  case ShuffleVector:  return "shufflevector";
     189lib/IR/Instructions.cpp://                      ShuffleVectorInst Implementation
     190lib/IR/Instructions.cpp:ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
     191lib/IR/Instructions.cpp:              ShuffleVector,
     192lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::op_begin(this),
     193lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::operands(this),
     194lib/IR/Instructions.cpp:         "Invalid shuffle vector instruction operands!");
     195lib/IR/Instructions.cpp:ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
     196lib/IR/Instructions.cpp:              ShuffleVector,
     197lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::op_begin(this),
     198lib/IR/Instructions.cpp:              OperandTraits<ShuffleVectorInst>::operands(this),
     199lib/IR/Instructions.cpp:         "Invalid shuffle vector instruction operands!");
     200lib/IR/Instructions.cpp:bool ShuffleVectorInst::isValidOperands(const Value *V1, const Value *V2,
     201lib/IR/Instructions.cpp:  // used as the shuffle mask. When this occurs, the shuffle mask will
     202lib/IR/Instructions.cpp:/// getMaskValue - Return the index from the shuffle mask for the specified
     203lib/IR/Instructions.cpp:int ShuffleVectorInst::getMaskValue(Constant *Mask, unsigned i) {
     204lib/IR/Instructions.cpp:/// getShuffleMask - Return the full mask for this instruction, where each
     205lib/IR/Instructions.cpp:void ShuffleVectorInst::getShuffleMask(Constant *Mask,
     206lib/IR/Instructions.cpp:ShuffleVectorInst *ShuffleVectorInst::clone_impl() const {
     207lib/IR/Instructions.cpp:  return new ShuffleVectorInst(getOperand(0), getOperand(1), getOperand(2));
     208lib/IR/LLVMContextImpl.cpp:void ShuffleVectorConstantExpr::anchor() { }
     209lib/IR/Verifier.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &EI);
     210lib/IR/Verifier.cpp:void Verifier::visitShuffleVectorInst(ShuffleVectorInst &SV) {
     211lib/IR/Verifier.cpp:  Assert1(ShuffleVectorInst::isValidOperands(SV.getOperand(0), SV.getOperand(1),
     212lib/IR/Verifier.cpp:          "Invalid shufflevector operands!", &SV);
     213Robs-MacBook-Pro:llvm cameron$
     214Robs-MacBook-Pro:llvm cameron$ fgrep huffle [li]*/*/*/*.*
     215include/llvm/ADT/IntervalMap.h:    assert(CurSize[n] == NewSize[n] && "Insufficient element shuffle");
     216include/llvm/Analysis/TargetFolder.h:  Constant *CreateShuffleVector(Constant *V1, Constant *V2,
     217include/llvm/Analysis/TargetFolder.h:    return Fold(ConstantExpr::getShuffleVector(V1, V2, Mask));
     218include/llvm/Analysis/TargetTransformInfo.h:  /// \brief The various kinds of shuffle patterns for vector queries.
     219include/llvm/Analysis/TargetTransformInfo.h:  enum ShuffleKind {
     220include/llvm/Analysis/TargetTransformInfo.h:  /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
     221include/llvm/Analysis/TargetTransformInfo.h:  /// extraction shuffle kinds.
     222include/llvm/Analysis/TargetTransformInfo.h:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, int Index = 0,
     223include/llvm/CodeGen/ISDOpcodes.h:    /// ShuffleVectorSDNode class.  This is quite similar to the Altivec
     224include/llvm/CodeGen/SelectionDAG.h:  /// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node.  The number of
     225include/llvm/CodeGen/SelectionDAG.h:  SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
     226include/llvm/CodeGen/SelectionDAGNodes.h:/// ShuffleVectorSDNode - This SDNode is used to implement the code generator
     227include/llvm/CodeGen/SelectionDAGNodes.h:/// support for the llvm IR shufflevector instruction.  It combines elements
     228include/llvm/CodeGen/SelectionDAGNodes.h:/// the shuffle mask.  For input vectors of width N, mask indices of 0..N-1
     229include/llvm/CodeGen/SelectionDAGNodes.h:class ShuffleVectorSDNode : public SDNode {
     230include/llvm/CodeGen/SelectionDAGNodes.h:  ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1,
     231include/llvm/IR/ConstantFolder.h:  Constant *CreateShuffleVector(Constant *V1, Constant *V2,
     232include/llvm/IR/ConstantFolder.h:    return ConstantExpr::getShuffleVector(V1, V2, Mask);
     233include/llvm/IR/Constants.h:  static Constant *getShuffleVector(Constant *V1, Constant *V2, Constant *Mask);
     234include/llvm/IR/IRBuilder.h:  Value *CreateShuffleVector(Value *V1, Value *V2, Value *Mask,
     235include/llvm/IR/IRBuilder.h:          return Insert(Folder.CreateShuffleVector(V1C, V2C, MC), Name);
     236include/llvm/IR/IRBuilder.h:    return Insert(new ShuffleVectorInst(V1, V2, Mask), Name);
     237include/llvm/IR/IRBuilder.h:    // First insert it into an undef vector so we can shuffle it.
     238include/llvm/IR/IRBuilder.h:    // Shuffle the value across the desired number of elements.
     239include/llvm/IR/IRBuilder.h:    return CreateShuffleVector(V, Undef, Zeros, Name + ".splat");
     240include/llvm/IR/InstVisitor.h:  RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction);}
     241include/llvm/IR/Instruction.def:HANDLE_OTHER_INST(56, ShuffleVector, ShuffleVectorInst)  // shuffle two vectors.
     242include/llvm/IR/Instructions.h://                           ShuffleVectorInst Class
     243include/llvm/IR/Instructions.h:/// ShuffleVectorInst - This instruction constructs a fixed permutation of two
     244include/llvm/IR/Instructions.h:class ShuffleVectorInst : public Instruction {
     245include/llvm/IR/Instructions.h:  ShuffleVectorInst *clone_impl() const override;
     246include/llvm/IR/Instructions.h:  ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
     247include/llvm/IR/Instructions.h:  ShuffleVectorInst(Value *V1, Value *V2, Value *Mask,
     248include/llvm/IR/Instructions.h:  /// isValidOperands - Return true if a shufflevector instruction can be
     249include/llvm/IR/Instructions.h:  /// getMaskValue - Return the index from the shuffle mask for the specified
     250include/llvm/IR/Instructions.h:  /// getShuffleMask - Return the full mask for this instruction, where each
     251include/llvm/IR/Instructions.h:  static void getShuffleMask(Constant *Mask, SmallVectorImpl<int> &Result);
     252include/llvm/IR/Instructions.h:  void getShuffleMask(SmallVectorImpl<int> &Result) const {
     253include/llvm/IR/Instructions.h:    return getShuffleMask(getMask(), Result);
     254include/llvm/IR/Instructions.h:  SmallVector<int, 16> getShuffleMask() const {
     255include/llvm/IR/Instructions.h:    getShuffleMask(Mask);
     256include/llvm/IR/Instructions.h:    return I->getOpcode() == Instruction::ShuffleVector;
     257include/llvm/IR/Instructions.h:struct OperandTraits<ShuffleVectorInst> :
     258include/llvm/IR/Instructions.h:  public FixedNumOperandTraits<ShuffleVectorInst, 3> {
     259include/llvm/IR/Instructions.h:DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorInst, Value)
     260include/llvm/IR/IntrinsicsPowerPC.td:  // vpkuhum is lowered to a shuffle.
     261include/llvm/IR/IntrinsicsPowerPC.td:  // vpkuwum is lowered to a shuffle.
     262include/llvm/IR/IntrinsicsX86.td:// Shuffle ops
     263include/llvm/IR/NoFolder.h:  Instruction *CreateShuffleVector(Constant *V1, Constant *V2,
     264include/llvm/IR/NoFolder.h:    return new ShuffleVectorInst(V1, V2, Mask);
     265include/llvm/Target/TargetLowering.h:  virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
     266include/llvm/Target/TargetLowering.h:  /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
     267include/llvm/Target/TargetSelectionDAG.td:def SDTVecShuffle : SDTypeProfile<1, 2, [
     268include/llvm/Target/TargetSelectionDAG.td:def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
     269lib/Bitcode/Reader/BitcodeReader.cpp:      V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
     270lib/Bitcode/Reader/BitcodeReader.cpp:      V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
     271lib/Bitcode/Reader/BitcodeReader.cpp:      I = new ShuffleVectorInst(Vec1, Vec2, Mask);
     272lib/Bitcode/Writer/BitcodeWriter.cpp:      case Instruction::ShuffleVector:
     273lib/Bitcode/Writer/BitcodeWriter.cpp:        // standard shufflevector instruction.  If the types are different,
     274lib/Bitcode/Writer/BitcodeWriter.cpp:        // then the shuffle is widening or truncating the input vectors, and
     275lib/Bitcode/Writer/BitcodeWriter.cpp:  case Instruction::ShuffleVector:
     276lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    SDValue XformToShuffleWithZero(SDNode *N);
     277lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
     278lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // If both shuffles use the same mask, and both shuffle within a single
     279lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // vector types from memory. In many cases this allows additional shuffle
     280lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
     281lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
     282lib/CodeGen/SelectionDAG/DAGCombiner.cpp:           "Inputs to shuffles are not the same type");
     283lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // Check that both shuffles use the same mask. The masks are known to be of
     284lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      return DAG.getVectorShuffle(VT, SDLoc(N), Op,
     285lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
     286lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Perform only after legalization to ensure build_vector / vector_shuffle
     287lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
     288lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    const ShuffleVectorSDNode *SVN = NULL;
     289lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
     290lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
     291lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // using shuffles.
     292lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // turn into a single shuffle instruction.
     293lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // at most two distinct vectors, turn this into a shuffle node.
     294lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // May only combine to shuffle after legalize if shuffle is legal.
     295lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // If everything is good, we can make a shuffle operation.
     296lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // We can't generate a shuffle node with mismatched input and output types.
     297lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
     298lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
     299lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // inputs come from at most two distinct vectors, turn this into a shuffle
     300lib/CodeGen/SelectionDAG/DAGCombiner.cpp:// Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
     301lib/CodeGen/SelectionDAG/DAGCombiner.cpp:static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
     302lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
     303lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
     304lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Canonicalize shuffle undef, undef -> undef
     305lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
     306lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Canonicalize shuffle v, v -> v, undef
     307lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
     308lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // Canonicalize shuffle undef, v -> v, undef.  Commute the shuffle mask.
     309lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
     310lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
     311lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    SDValue V = partitionShuffleOfConcats(N, DAG);
     312lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // If this shuffle node is simply a swizzle of another shuffle node,
     313lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // and it reverses the swizzle of the previous shuffle then we can
     314lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  // optimize shuffle(shuffle(x, undef), undef) -> x.
     315lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
     316lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // Shuffle nodes can only reverse shuffles with a single non-undef value.
     317lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // The incoming shuffle must be of the same type as the result of the
     318lib/CodeGen/SelectionDAG/DAGCombiner.cpp:    // current shuffle.
     319lib/CodeGen/SelectionDAG/DAGCombiner.cpp:           "Shuffle types don't match");
     320lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // shuffle. Adopt the incoming index.
     321lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // The combined shuffle must map each index to itself.
     322lib/CodeGen/SelectionDAG/DAGCombiner.cpp:/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
     323lib/CodeGen/SelectionDAG/DAGCombiner.cpp:/// an AND to a vector_shuffle with the destination vector and a zero vector.
     324lib/CodeGen/SelectionDAG/DAGCombiner.cpp:///      vector_shuffle V, Zero, <0, 4, 2, 4>
     325lib/CodeGen/SelectionDAG/DAGCombiner.cpp:SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
     326lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      // Let's see if the target supports this vector_shuffle.
     327lib/CodeGen/SelectionDAG/DAGCombiner.cpp:      SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
     328lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  SDValue Shuffle = XformToShuffleWithZero(N);
     329lib/CodeGen/SelectionDAG/DAGCombiner.cpp:  if (Shuffle.getNode()) return Shuffle;
     330lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
     331lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  /// whose vector element type is narrower than the original shuffle type.
     332lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
     333lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
     334lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:/// whose vector element type is narrower than the original shuffle type.
     335lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT,  SDLoc dl,
     336lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
     337lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
     338lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:  return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
     339lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      // We generate a shuffle of InVec and ScVec, so the shuffle mask
     340lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
     341lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    SmallVector<int, 8> ShuffleVec(NumElems, -1);
     342lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      ShuffleVec[i] = V == Value1 ? 0 : NumElems;
     343lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
     344lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      // Return shuffle(LowValVec, undef, <0,0,0,0>)
     345lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:      return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
     346lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
     347lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:        // Convert shuffle node.
     348lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:        // Convert the shuffle mask
     349lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
     350lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    // Convert the shuffle mask to the right # elements.
     351lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:    Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
     352lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
     353lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:  return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
     354lib/CodeGen/SelectionDAG/LegalizeTypes.h:  void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
     355lib/CodeGen/SelectionDAG/LegalizeTypes.h:  SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
     356lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
     357lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
     358lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:  // express it as a vector shuffle of those two inputs.  Otherwise extract the
     359lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    // Build a shuffle mask for the output, discovering on the fly which
     360lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    // input vectors to use as shuffle operands (recorded in InputUsed).
     361lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    // If building a suitable shuffle vector proves too hard, then bail
     362lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      // Find or create a shuffle vector operand to hold this input.
     363lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:        // shuffle vector.  Insert all elements into a BUILD_VECTOR instead.
     364lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      // Add the mask index for the new shuffle vector.
     365lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      // At least one input vector was used.  Create a new shuffle vector.
     366lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:      Output =  DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
     367lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:    Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
     368lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:        // Replace concat of two operands with a shuffle.
     369lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:        return DAG.getVectorShuffle(WidenVT, dl,
     370lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
     371lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:  return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
     372lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
     373lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  assert(!isa<ShuffleVectorSDNode>(N) && "Bad ShuffleVectorSDNode!");
     374lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    // vector shuffle in this situation). However, we do not need any code to
     375lib/CodeGen/SelectionDAG/SelectionDAG.cpp:// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in
     376lib/CodeGen/SelectionDAG/SelectionDAG.cpp:// the shuffle mask M that point at N1 to point at N2, and indices that point
     377lib/CodeGen/SelectionDAG/SelectionDAG.cpp:static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
     378lib/CodeGen/SelectionDAG/SelectionDAG.cpp:SDValue SelectionDAG::getVectorShuffle(EVT VT, SDLoc dl, SDValue N1,
     379lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize shuffle undef, undef -> undef
     380lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // input to the shuffle.
     381lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize shuffle v, v -> v, undef
     382lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize shuffle undef, v -> v, undef.  Commute the shuffle mask.
     383lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    commuteShuffle(N1, N2, MaskVec);
     384lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize all index into lhs, -> shuffle lhs, undef
     385lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Canonicalize all index into rhs, -> shuffle rhs, undef
     386lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    commuteShuffle(N1, N2, MaskVec);
     387lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // If Identity shuffle return that node.
     388lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  ShuffleVectorSDNode *N =
     389lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    new (NodeAllocator) ShuffleVectorSDNode(VT, dl.getIROrder(),
     390lib/CodeGen/SelectionDAG/SelectionDAG.cpp:    llvm_unreachable("should use getVectorShuffle constructor!");
     391lib/CodeGen/SelectionDAG/SelectionDAG.cpp:bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) {
     392lib/CodeGen/SelectionDAG/SelectionDAG.cpp:  // Find the first non-undef value in the shuffle mask.
     393lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:      // Vector widening case, e.g. <2 x float> -> <4 x float>.  Shuffle in
     394lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:// Utility for visitShuffleVector - Return true if every element in Mask,
     395lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:void SelectionDAGBuilder::visitShuffleVector(const User &I) {
     396lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:  ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
     397lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:    setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
     398lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:  // Normalize the shuffle vector since mask and vector length don't match.
     399lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:        // The shuffle is concatenating two vectors together.
     400lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:        // The shuffle is concatenating two vectors together.
     401lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:    setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
     402lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:    // two subvectors and do the shuffle. The analysis is done by calculating
     403lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:      // Extract appropriate subvector and generate a vector shuffle
     404lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:      setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
     405lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:  // replacing the shuffle with extract and build vector.
     406lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h:class ShuffleVectorInst;
     407lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h:  void visitShuffleVector(const User &I);
     408lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp:  case ISD::VECTOR_SHUFFLE:             return "vector_shuffle";
     409lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp:  } else if (const ShuffleVectorSDNode *SVN =
     410lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp:               dyn_cast<ShuffleVectorSDNode>(this)) {
     411lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
     412lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:  case Instruction::ShuffleVector:  NumFastIselFailShuffleVector++; return;
     413lib/ExecutionEngine/Interpreter/Execution.cpp:void Interpreter::visitShuffleVectorInst(ShuffleVectorInst &I){
     414lib/ExecutionEngine/Interpreter/Execution.cpp:    llvm_unreachable("Unhandled dest type for shufflevector instruction");
     415lib/ExecutionEngine/Interpreter/Execution.cpp:  // shufflevector instruction.
     416lib/ExecutionEngine/Interpreter/Execution.cpp:          // %tmp = shufflevector <2 x i32> <i32 3, i32 4>, <2 x i32> undef,
     417lib/ExecutionEngine/Interpreter/Execution.cpp:          llvm_unreachable("Invalid mask in shufflevector instruction");
     418lib/ExecutionEngine/Interpreter/Execution.cpp:          llvm_unreachable("Invalid mask in shufflevector instruction");
     419lib/ExecutionEngine/Interpreter/Execution.cpp:          llvm_unreachable("Invalid mask in shufflevector instruction");
     420lib/ExecutionEngine/Interpreter/Interpreter.h:  void visitShuffleVectorInst(ShuffleVectorInst &I);
     421lib/Target/AArch64/AArch64ISelLowering.cpp:  SDValue ShuffleVec
     422lib/Target/AArch64/AArch64ISelLowering.cpp:    = DAG.getVectorShuffle(DestVT, SDLoc(N), Sext, DAG.getUNDEF(DestVT), Mask);
     423lib/Target/AArch64/AArch64ISelLowering.cpp:                SubRegVT, ShuffleVec,
     424lib/Target/AArch64/AArch64ISelLowering.cpp:// Check whether a shuffle_vector could be presented as concat_vector.
     425lib/Target/AArch64/AArch64ISelLowering.cpp:// Check whether a Build Vector could be presented as Shuffle Vector.
     426lib/Target/AArch64/AArch64ISelLowering.cpp:// This Shuffle Vector maybe not legalized, so the length of its operand and
     427lib/Target/AArch64/AArch64ISelLowering.cpp:bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
     428lib/Target/AArch64/AArch64ISelLowering.cpp:  // Try to lower this in lowering ShuffleVector way.
     429lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isKnownShuffleVector(Op, DAG, V0, V1, Mask)) {
     430lib/Target/AArch64/AArch64ISelLowering.cpp:      SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
     431lib/Target/AArch64/AArch64ISelLowering.cpp:      if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
     432lib/Target/AArch64/AArch64ISelLowering.cpp:        return Shuffle;
     433lib/Target/AArch64/AArch64ISelLowering.cpp:        return LowerVECTOR_SHUFFLE(Shuffle, DAG);
     434lib/Target/AArch64/AArch64ISelLowering.cpp:  // scalar_to_vector for the elements followed by a shuffle (provided the
     435lib/Target/AArch64/AArch64ISelLowering.cpp:  // shuffle is valid for the target) and materialization element by element
     436lib/Target/AArch64/AArch64ISelLowering.cpp:/// isREVMask - Check if a vector shuffle corresponds to a REV
     437lib/Target/AArch64/AArch64ISelLowering.cpp:  // If the first shuffle index is UNDEF, be optimistic.
     438lib/Target/AArch64/AArch64ISelLowering.cpp:// isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and
     439lib/Target/AArch64/AArch64ISelLowering.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
     440lib/Target/AArch64/AArch64ISelLowering.cpp:  // Convert shuffles that are directly supported on NEON to target-specific
     441lib/Target/AArch64/AArch64ISelLowering.cpp:  // DAG nodes, instead of keeping them as shuffles and matching them again
     442lib/Target/AArch64/AArch64ISelLowering.cpp:  ArrayRef<int> ShuffleMask = SVN->getMask();
     443lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isREVMask(ShuffleMask, VT, 64))
     444lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isREVMask(ShuffleMask, VT, 32))
     445lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isREVMask(ShuffleMask, VT, 16))
     446lib/Target/AArch64/AArch64ISelLowering.cpp:    ISDNo = isPermuteMask(ShuffleMask, VT, true);
     447lib/Target/AArch64/AArch64ISelLowering.cpp:    ISDNo = isPermuteMask(ShuffleMask, VT, false);
     448lib/Target/AArch64/AArch64ISelLowering.cpp:  if (isConcatVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
     449lib/Target/AArch64/AArch64ISelLowering.cpp:  // If the element of shuffle mask are all the same constant, we can
     450lib/Target/AArch64/AArch64ISelLowering.cpp:  if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
     451lib/Target/AArch64/AArch64ISelLowering.cpp:  int Length = ShuffleMask.size();
     452lib/Target/AArch64/AArch64ISelLowering.cpp:  // If the number of v1 elements is the same as the number of shuffle mask
     453lib/Target/AArch64/AArch64ISelLowering.cpp:  // element and the shuffle masks are sequential values, we can transform
     454lib/Target/AArch64/AArch64ISelLowering.cpp:    // Check if the shuffle mask is sequential.
     455lib/Target/AArch64/AArch64ISelLowering.cpp:    while (ShuffleMask[SkipUndef] == -1) {
     456lib/Target/AArch64/AArch64ISelLowering.cpp:    int CurMask = ShuffleMask[SkipUndef];
     457lib/Target/AArch64/AArch64ISelLowering.cpp:        if (ShuffleMask[I] != -1 && ShuffleMask[I] != CurMask) {
     458lib/Target/AArch64/AArch64ISelLowering.cpp:        unsigned Index = (EltSize / 8) * (ShuffleMask[SkipUndef] - SkipUndef);
     459lib/Target/AArch64/AArch64ISelLowering.cpp:  // For shuffle mask like "0, 1, 2, 3, 4, 5, 13, 7", try to generate insert
     460lib/Target/AArch64/AArch64ISelLowering.cpp:  // If shuffle mask is like "0, 1, 10, 11, 12, 13, 14, 15", V2 would be a
     461lib/Target/AArch64/AArch64ISelLowering.cpp:    if (ShuffleMask[I] != I) {
     462lib/Target/AArch64/AArch64ISelLowering.cpp:      NV1Elt.push_back(ShuffleMask[I]);
     463lib/Target/AArch64/AArch64ISelLowering.cpp:    if (ShuffleMask[I] != (I + V1EltNum)) {
     464lib/Target/AArch64/AArch64ISelLowering.cpp:      NV2Elt.push_back(ShuffleMask[I]);
     465lib/Target/AArch64/AArch64ISelLowering.h:  bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &V0,
     466lib/Target/ARM/ARMISelLowering.cpp:#include "ARMPerfectShuffle.h"
     467lib/Target/ARM/ARMISelLowering.cpp:// check if an VEXT instruction can handle the shuffle mask when the
     468lib/Target/ARM/ARMISelLowering.cpp:// vector sources of the shuffle are the same.
     469lib/Target/ARM/ARMISelLowering.cpp:  // Assume that the first shuffle index is not UNDEF.  Fail if it is.
     470lib/Target/ARM/ARMISelLowering.cpp:  // If this is a VEXT shuffle, the immediate value is the index of the first
     471lib/Target/ARM/ARMISelLowering.cpp:  // element.  The other shuffle indices must be the successive elements after
     472lib/Target/ARM/ARMISelLowering.cpp:  // Assume that the first shuffle index is not UNDEF.  Fail if it is.
     473lib/Target/ARM/ARMISelLowering.cpp:  // If this is a VEXT shuffle, the immediate value is the index of the first
     474lib/Target/ARM/ARMISelLowering.cpp:  // element.  The other shuffle indices must be the successive elements after
     475lib/Target/ARM/ARMISelLowering.cpp:/// isVREVMask - Check if a vector shuffle corresponds to a VREV
     476lib/Target/ARM/ARMISelLowering.cpp:  // If the first shuffle index is UNDEF, be optimistic.
     477lib/Target/ARM/ARMISelLowering.cpp:  // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
     478lib/Target/ARM/ARMISelLowering.cpp:/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
     479lib/Target/ARM/ARMISelLowering.cpp:/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
     480lib/Target/ARM/ARMISelLowering.cpp:/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
     481lib/Target/ARM/ARMISelLowering.cpp:    SDValue shuffle = ReconstructShuffle(Op, DAG);
     482lib/Target/ARM/ARMISelLowering.cpp:    if (shuffle != SDValue())
     483lib/Target/ARM/ARMISelLowering.cpp:      return shuffle;
     484lib/Target/ARM/ARMISelLowering.cpp:  // scalar_to_vector for the elements followed by a shuffle (provided the
     485lib/Target/ARM/ARMISelLowering.cpp:  // shuffle is valid for the target) and materialization element by element
     486lib/Target/ARM/ARMISelLowering.cpp:// shuffle in combination with VEXTs.
     487lib/Target/ARM/ARMISelLowering.cpp:SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
     488lib/Target/ARM/ARMISelLowering.cpp:      // A shuffle can only come from building a vector from various
     489lib/Target/ARM/ARMISelLowering.cpp:      // This code doesn't know how to handle shuffles where the vector
     490lib/Target/ARM/ARMISelLowering.cpp:  SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
     491lib/Target/ARM/ARMISelLowering.cpp:  // and prepares appropriate SDValues for a shuffle if possible.
     492lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = SourceVecs[i];
     493lib/Target/ARM/ARMISelLowering.cpp:      // break it down again in a shuffle.
     494lib/Target/ARM/ARMISelLowering.cpp:           "unexpected vector sizes in ReconstructShuffle");
     495lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
     496lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
     497lib/Target/ARM/ARMISelLowering.cpp:      ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
     498lib/Target/ARM/ARMISelLowering.cpp:  if (isShuffleMaskLegal(Mask, VT))
     499lib/Target/ARM/ARMISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
     500lib/Target/ARM/ARMISelLowering.cpp:/// isShuffleMaskLegal - Targets can use this to indicate that they only
     501lib/Target/ARM/ARMISelLowering.cpp:ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
     502lib/Target/ARM/ARMISelLowering.cpp:    // Compute the index in the perfect shuffle table.
     503lib/Target/ARM/ARMISelLowering.cpp:    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
     504lib/Target/ARM/ARMISelLowering.cpp:          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
     505lib/Target/ARM/ARMISelLowering.cpp:/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
     506lib/Target/ARM/ARMISelLowering.cpp:/// the specified operations to build the shuffle.
     507lib/Target/ARM/ARMISelLowering.cpp:static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
     508lib/Target/ARM/ARMISelLowering.cpp:  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
     509lib/Target/ARM/ARMISelLowering.cpp:  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
     510lib/Target/ARM/ARMISelLowering.cpp:  default: llvm_unreachable("Unknown shuffle opcode!");
     511lib/Target/ARM/ARMISelLowering.cpp:                                       ArrayRef<int> ShuffleMask,
     512lib/Target/ARM/ARMISelLowering.cpp:         I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
     513lib/Target/ARM/ARMISelLowering.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
     514lib/Target/ARM/ARMISelLowering.cpp:  // Convert shuffles that are directly supported on NEON to target-specific
     515lib/Target/ARM/ARMISelLowering.cpp:  // DAG nodes, instead of keeping them as shuffles and matching them again
     516lib/Target/ARM/ARMISelLowering.cpp:  ArrayRef<int> ShuffleMask = SVN->getMask();
     517lib/Target/ARM/ARMISelLowering.cpp:    if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
     518lib/Target/ARM/ARMISelLowering.cpp:    if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
     519lib/Target/ARM/ARMISelLowering.cpp:    if (isVREVMask(ShuffleMask, VT, 64))
     520lib/Target/ARM/ARMISelLowering.cpp:    if (isVREVMask(ShuffleMask, VT, 32))
     521lib/Target/ARM/ARMISelLowering.cpp:    if (isVREVMask(ShuffleMask, VT, 16))
     522lib/Target/ARM/ARMISelLowering.cpp:        isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
     523lib/Target/ARM/ARMISelLowering.cpp:    // Check for Neon shuffles that modify both input vectors in place.
     524lib/Target/ARM/ARMISelLowering.cpp:    // If both results are used, i.e., if there are two shuffles with the same
     525lib/Target/ARM/ARMISelLowering.cpp:    // used for both shuffles.
     526lib/Target/ARM/ARMISelLowering.cpp:    if (isVTRNMask(ShuffleMask, VT, WhichResult))
     527lib/Target/ARM/ARMISelLowering.cpp:    if (isVUZPMask(ShuffleMask, VT, WhichResult))
     528lib/Target/ARM/ARMISelLowering.cpp:    if (isVZIPMask(ShuffleMask, VT, WhichResult))
     529lib/Target/ARM/ARMISelLowering.cpp:    if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
     530lib/Target/ARM/ARMISelLowering.cpp:    if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
     531lib/Target/ARM/ARMISelLowering.cpp:    if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
     532lib/Target/ARM/ARMISelLowering.cpp:  // If the shuffle is not directly supported and it has 4 elements, use
     533lib/Target/ARM/ARMISelLowering.cpp:  // the PerfectShuffle-generated table to synthesize it from other shuffles.
     534lib/Target/ARM/ARMISelLowering.cpp:      if (ShuffleMask[i] < 0)
     535lib/Target/ARM/ARMISelLowering.cpp:        PFIndexes[i] = ShuffleMask[i];
     536lib/Target/ARM/ARMISelLowering.cpp:    // Compute the index in the perfect shuffle table.
     537lib/Target/ARM/ARMISelLowering.cpp:    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
     538lib/Target/ARM/ARMISelLowering.cpp:      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
     539lib/Target/ARM/ARMISelLowering.cpp:  // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
     540lib/Target/ARM/ARMISelLowering.cpp:      if (ShuffleMask[i] < 0)
     541lib/Target/ARM/ARMISelLowering.cpp:                                  ShuffleMask[i] < (int)NumElts ? V1 : V2,
     542lib/Target/ARM/ARMISelLowering.cpp:                                  DAG.getConstant(ShuffleMask[i] & (NumElts-1),
     543lib/Target/ARM/ARMISelLowering.cpp:  if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
     544lib/Target/ARM/ARMISelLowering.cpp:    SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
     545lib/Target/ARM/ARMISelLowering.cpp:  // Optimize trunc store (of multiple scalars) to shuffle and store.  First,
     546lib/Target/ARM/ARMISelLowering.cpp:    // Create a type on which we perform the shuffle.
     547lib/Target/ARM/ARMISelLowering.cpp:    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
     548lib/Target/ARM/ARMISelLowering.cpp:    for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
     549lib/Target/ARM/ARMISelLowering.cpp:    // Can't shuffle using an illegal type.
     550lib/Target/ARM/ARMISelLowering.cpp:    SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
     551lib/Target/ARM/ARMISelLowering.cpp:                                ShuffleVec.data());
     552lib/Target/ARM/ARMISelLowering.cpp:  // The LLVM shufflevector instruction does not require the shuffle mask
     553lib/Target/ARM/ARMISelLowering.cpp:  //   shuffle(concat(v1, undef), concat(v2, undef)) ->
     554lib/Target/ARM/ARMISelLowering.cpp:  //   shuffle(concat(v1, v2), undef)
     555lib/Target/ARM/ARMISelLowering.cpp:  // Translate the shuffle mask.
     556lib/Target/ARM/ARMISelLowering.cpp:  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
     557lib/Target/ARM/ARMISelLowering.cpp:  return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
     558lib/Target/ARM/ARMISelLowering.h:      // Vector shuffles:
     559lib/Target/ARM/ARMISelLowering.h:      VTBL1,        // 1-register shuffle with mask
     560lib/Target/ARM/ARMISelLowering.h:      VTBL2,        // 2-register shuffle with mask
     561lib/Target/ARM/ARMISelLowering.h:      // is fine if BUILD_VECTORs are always lowered to shuffles or other
     562lib/Target/ARM/ARMISelLowering.h:    bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
     563lib/Target/ARM/ARMISelLowering.h:    SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
     564lib/Target/ARM/ARMInstrNEON.td:// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
     565lib/Target/ARM/ARMInstrNEON.td:class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
     566lib/Target/ARM/ARMInstrNEON.td:class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
     567lib/Target/ARM/ARMInstrNEON.td:// Other Vector Shuffles.
     568lib/Target/ARM/ARMInstrNEON.td:def  VTRNd8   : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
     569lib/Target/ARM/ARMInstrNEON.td:def  VTRNd16  : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
     570lib/Target/ARM/ARMInstrNEON.td:def  VTRNd32  : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
     571lib/Target/ARM/ARMInstrNEON.td:def  VTRNq8   : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
     572lib/Target/ARM/ARMInstrNEON.td:def  VTRNq16  : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
     573lib/Target/ARM/ARMInstrNEON.td:def  VTRNq32  : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
     574lib/Target/ARM/ARMInstrNEON.td:def  VUZPd8   : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
     575lib/Target/ARM/ARMInstrNEON.td:def  VUZPd16  : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
     576lib/Target/ARM/ARMInstrNEON.td:def  VUZPq8   : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
     577lib/Target/ARM/ARMInstrNEON.td:def  VUZPq16  : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
     578lib/Target/ARM/ARMInstrNEON.td:def  VUZPq32  : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
     579lib/Target/ARM/ARMInstrNEON.td:def  VZIPd8   : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
     580lib/Target/ARM/ARMInstrNEON.td:def  VZIPd16  : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
     581lib/Target/ARM/ARMInstrNEON.td:def  VZIPq8   : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
     582lib/Target/ARM/ARMInstrNEON.td:def  VZIPq16  : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
     583lib/Target/ARM/ARMInstrNEON.td:def  VZIPq32  : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
     584lib/Target/ARM/ARMPerfectShuffle.h://===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table --------*- C++ -*-===//
     585lib/Target/ARM/ARMPerfectShuffle.h:// This file, which was autogenerated by llvm-PerfectShuffle, contains data
     586lib/Target/ARM/ARMPerfectShuffle.h:// for the optimal way to build a perfect shuffle using neon instructions.
     587lib/Target/ARM/ARMPerfectShuffle.h:static const unsigned PerfectShuffleTable[6561+1] = {
     588lib/Target/ARM/ARMTargetTransformInfo.cpp:  unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
     589lib/Target/ARM/ARMTargetTransformInfo.cpp:unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
     590lib/Target/ARM/ARMTargetTransformInfo.cpp:  // We only handle costs of reverse shuffles for now.
     591lib/Target/ARM/ARMTargetTransformInfo.cpp:    return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
     592lib/Target/ARM/ARMTargetTransformInfo.cpp:  static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
     593lib/Target/ARM/ARMTargetTransformInfo.cpp:    // Reverse shuffle cost one instruction if we are shuffling within a double
     594lib/Target/ARM/ARMTargetTransformInfo.cpp:    // word (vrev) or two if we shuffle a quad word (vrev, vext).
     595lib/Target/ARM/ARMTargetTransformInfo.cpp:  int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
     596lib/Target/ARM/ARMTargetTransformInfo.cpp:    return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
     597lib/Target/ARM/ARMTargetTransformInfo.cpp:  return LT.first * NEONShuffleTbl[Idx].Cost;
     598lib/Target/CppBackend/CPPBackend.cpp:      case Instruction::ShuffleVector:  Out << "getShuffleVector("; break;
     599lib/Target/CppBackend/CPPBackend.cpp:  case Instruction::ShuffleVector: {
     600lib/Target/CppBackend/CPPBackend.cpp:    const ShuffleVectorInst* svi = cast<ShuffleVectorInst>(I);
     601lib/Target/CppBackend/CPPBackend.cpp:    Out << "ShuffleVectorInst* " << getCppName(svi)
     602lib/Target/CppBackend/CPPBackend.cpp:        << " = new ShuffleVectorInst(" << opNames[0]
     603lib/Target/Hexagon/HexagonIntrinsics.td:// STYPE / PERM / Vector shuffle.
     604lib/Target/Mips/MSA.txt:        It is not possible to emit vshf.w when the shuffle description is
     605lib/Target/Mips/MSA.txt:        instead. It is also impossible for the shuffle description to be
     606lib/Target/Mips/MSA.txt:        unknown at compile-time due to the definition of shufflevector in
     607lib/Target/Mips/MSA.txt:        When the shuffle description describes a splat operation, splat.[bhwd]
     608lib/Target/Mips/MSA.txt:        same shuffle. ilvev.d will be emitted instead.
     609lib/Target/Mips/MSA.txt:        same shuffle. ilvod.d will be emitted instead.
     610lib/Target/Mips/MipsISelLowering.h:      // Vector Shuffle with mask as an operand
     611lib/Target/Mips/MipsISelLowering.h:      VSHF,  // Generic shuffle
     612lib/Target/Mips/MipsISelLowering.h:      SHF,   // 4-element set shuffle.
     613lib/Target/Mips/MipsMSAInstrInfo.td:// Big endian bitcasts expand to shuffle instructions.
     614lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
     615lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
     616lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
     617lib/Target/Mips/MipsSEISelDAGToDAG.cpp://       sometimes a shuffle in big-endian mode.
     618lib/Target/Mips/MipsSEISelLowering.cpp:    // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
     619lib/Target/Mips/MipsSEISelLowering.cpp:// SHF splits the vector into blocks of four elements, then shuffles these
     620lib/Target/Mips/MipsSEISelLowering.cpp://   %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
     621lib/Target/Mips/MipsSEISelLowering.cpp:// This mostly consists of converting the shuffle indices in Indices into a
     622lib/Target/Mips/MipsSEISelLowering.cpp:    llvm_unreachable("shuffle vector mask references neither vector operand?");
     623lib/Target/Mips/MipsSEISelLowering.cpp:// indices in the shuffle.
     624lib/Target/Mips/MipsSEISelLowering.cpp:  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
     625lib/Target/Mips/MipsSEISelLowering.h:    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
     626lib/Target/Mips/MipsSEISelLowering.h:    /// depending on the indices in the shuffle.
     627lib/Target/NVPTX/NVPTX.h:  VecShuffle = 4,
     628lib/Target/NVPTX/NVPTXGenericToNVVM.cpp:  case Instruction::ShuffleVector:
     629lib/Target/NVPTX/NVPTXGenericToNVVM.cpp:    // ShuffleVector
     630lib/Target/NVPTX/NVPTXGenericToNVVM.cpp:    return Builder.CreateShuffleVector(NewOperands[0], NewOperands[1],
     631lib/Target/NVPTX/NVPTXInstrInfo.td:def isVecShuffle : VecInstTypeEnum<4>;
     632lib/Target/NVPTX/NVPTXVector.td:class ShuffleOneLine<string vecsize, string elem, string type>
     633lib/Target/NVPTX/NVPTXVector.td:class ShuffleAsmStr2<string type>
     634lib/Target/NVPTX/NVPTXVector.td:  string t1 = ShuffleOneLine<"2", "0", type>.s;
     635lib/Target/NVPTX/NVPTXVector.td:  string s  = !strconcat(t2, ShuffleOneLine<"2", "1", type>.s);
     636lib/Target/NVPTX/NVPTXVector.td:class ShuffleAsmStr4<string type>
     637lib/Target/NVPTX/NVPTXVector.td:  string t1 = ShuffleOneLine<"4", "0", type>.s;
     638lib/Target/NVPTX/NVPTXVector.td:  string t3 = !strconcat(t2, ShuffleOneLine<"4", "1", type>.s);
     639lib/Target/NVPTX/NVPTXVector.td:  string t5 = !strconcat(t4, ShuffleOneLine<"4", "2", type>.s);
     640lib/Target/NVPTX/NVPTXVector.td:  string s  = !strconcat(t6, ShuffleOneLine<"4", "3", type>.s);
     641lib/Target/NVPTX/NVPTXVector.td:let neverHasSideEffects=1, VecInstType=isVecShuffle.Value in {
     642lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4f32 : NVPTXVecInst<(outs V4F32Regs:$dst),
     643lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"f32">.s),
     644lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4i32 : NVPTXVecInst<(outs V4I32Regs:$dst),
     645lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"u32">.s),
     646lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4i16 : NVPTXVecInst<(outs V4I16Regs:$dst),
     647lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"u16">.s),
     648lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v4i8 : NVPTXVecInst<(outs V4I8Regs:$dst),
     649lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr4<"u16">.s),
     650lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2f32 : NVPTXVecInst<(outs V2F32Regs:$dst),
     651lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"f32">.s),
     652lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i32 : NVPTXVecInst<(outs V2I32Regs:$dst),
     653lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u32">.s),
     654lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i8 : NVPTXVecInst<(outs V2I8Regs:$dst),
     655lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u16">.s),
     656lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i16 : NVPTXVecInst<(outs V2I16Regs:$dst),
     657lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u16">.s),
     658lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2f64 : NVPTXVecInst<(outs V2F64Regs:$dst),
     659lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"f64">.s),
     660lib/Target/NVPTX/NVPTXVector.td:def VecShuffle_v2i64 : NVPTXVecInst<(outs V2I64Regs:$dst),
     661lib/Target/NVPTX/NVPTXVector.td:                                 ShuffleAsmStr2<"u64">.s),
     662lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask0 : SDNodeXForm<vector_shuffle, [{
     663lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
     664lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask1 : SDNodeXForm<vector_shuffle, [{
     665lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
     666lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask2 : SDNodeXForm<vector_shuffle, [{
     667lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
     668lib/Target/NVPTX/NVPTXVector.td:def ShuffleMask3 : SDNodeXForm<vector_shuffle, [{
     669lib/Target/NVPTX/NVPTXVector.td:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
     670lib/Target/NVPTX/NVPTXVector.td:                       (vector_shuffle node:$lhs, node:$rhs),
     671lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2f64 V2F64Regs:$src1, V2F64Regs:$src2,
     672lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
     673lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4f32 V4F32Regs:$src1, V4F32Regs:$src2,
     674lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
     675lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
     676lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2f32 V2F32Regs:$src1, V2F32Regs:$src2,
     677lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
     678lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i64 V2I64Regs:$src1, V2I64Regs:$src2,
     679lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
     680lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4i32 V4I32Regs:$src1, V4I32Regs:$src2,
     681lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
     682lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
     683lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i32 V2I32Regs:$src1, V2I32Regs:$src2,
     684lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
     685lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4i16 V4I16Regs:$src1, V4I16Regs:$src2,
     686lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
     687lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
     688lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i16 V2I16Regs:$src1, V2I16Regs:$src2,
     689lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
     690lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v4i8 V4I8Regs:$src1, V4I8Regs:$src2,
     691lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op),
     692lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask2 node:$op), (ShuffleMask3 node:$op))>;
     693lib/Target/NVPTX/NVPTXVector.td:          (VecShuffle_v2i8 V2I8Regs:$src1, V2I8Regs:$src2,
     694lib/Target/NVPTX/NVPTXVector.td:                            (ShuffleMask0 node:$op), (ShuffleMask1 node:$op))>;
     695lib/Target/PowerPC/PPCISelLowering.cpp:#include "PPCPerfectShuffle.h"
     696lib/Target/PowerPC/PPCISelLowering.cpp:      // We promote all shuffles to v16i8.
     697lib/Target/PowerPC/PPCISelLowering.cpp:/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
     698lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
     699lib/Target/PowerPC/PPCISelLowering.cpp:/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
     700lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
     701lib/Target/PowerPC/PPCISelLowering.cpp:/// isVMerge - Common function, used to match vmrg* shuffles.
     702lib/Target/PowerPC/PPCISelLowering.cpp:static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
     703lib/Target/PowerPC/PPCISelLowering.cpp:         "PPC only supports shuffles by bytes!");
     704lib/Target/PowerPC/PPCISelLowering.cpp:/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
     705lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
     706lib/Target/PowerPC/PPCISelLowering.cpp:/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
     707lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
     708lib/Target/PowerPC/PPCISelLowering.cpp:/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
     709lib/Target/PowerPC/PPCISelLowering.cpp:int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
     710lib/Target/PowerPC/PPCISelLowering.cpp:         "PPC only supports shuffles by bytes!");
     711lib/Target/PowerPC/PPCISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
     712lib/Target/PowerPC/PPCISelLowering.cpp:  // Find the first non-undef value in the shuffle mask.
     713lib/Target/PowerPC/PPCISelLowering.cpp:/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
     714lib/Target/PowerPC/PPCISelLowering.cpp:bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
     715lib/Target/PowerPC/PPCISelLowering.cpp:/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
     716lib/Target/PowerPC/PPCISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
     717lib/Target/PowerPC/PPCISelLowering.cpp:  assert(isSplatShuffleMask(SVOp, EltSize));
     718lib/Target/PowerPC/PPCISelLowering.cpp:  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
     719lib/Target/PowerPC/PPCISelLowering.cpp:/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
     720lib/Target/PowerPC/PPCISelLowering.cpp:/// the specified operations to build the shuffle.
     721lib/Target/PowerPC/PPCISelLowering.cpp:static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
     722lib/Target/PowerPC/PPCISelLowering.cpp:  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
     723lib/Target/PowerPC/PPCISelLowering.cpp:  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
     724lib/Target/PowerPC/PPCISelLowering.cpp:  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
     725lib/Target/PowerPC/PPCISelLowering.cpp:/// is a shuffle we can handle in a single instruction, return it.  Otherwise,
     726lib/Target/PowerPC/PPCISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     727lib/Target/PowerPC/PPCISelLowering.cpp:    if (PPC::isSplatShuffleMask(SVOp, 1) ||
     728lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isSplatShuffleMask(SVOp, 2) ||
     729lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isSplatShuffleMask(SVOp, 4) ||
     730lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVPKUWUMShuffleMask(SVOp, true) ||
     731lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVPKUHUMShuffleMask(SVOp, true) ||
     732lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
     733lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
     734lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
     735lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
     736lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
     737lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
     738lib/Target/PowerPC/PPCISelLowering.cpp:        PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
     739lib/Target/PowerPC/PPCISelLowering.cpp:  // Altivec has a variety of "shuffle immediates" that take two vector inputs
     740lib/Target/PowerPC/PPCISelLowering.cpp:  if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
     741lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVPKUHUMShuffleMask(SVOp, false) ||
     742lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
     743lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
     744lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
     745lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
     746lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
     747lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
     748lib/Target/PowerPC/PPCISelLowering.cpp:      PPC::isVMRGHShuffleMask(SVOp, 4, false))
     749lib/Target/PowerPC/PPCISelLowering.cpp:  // Check to see if this is a shuffle of 4-byte values.  If so, we can use our
     750lib/Target/PowerPC/PPCISelLowering.cpp:  // perfect shuffle table to emit an optimal matching sequence.
     751lib/Target/PowerPC/PPCISelLowering.cpp:  bool isFourElementShuffle = true;
     752lib/Target/PowerPC/PPCISelLowering.cpp:  for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
     753lib/Target/PowerPC/PPCISelLowering.cpp:        isFourElementShuffle = false;
     754lib/Target/PowerPC/PPCISelLowering.cpp:        isFourElementShuffle = false;
     755lib/Target/PowerPC/PPCISelLowering.cpp:  // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
     756lib/Target/PowerPC/PPCISelLowering.cpp:  // perfect shuffle vector to determine if it is cost effective to do this as
     757lib/Target/PowerPC/PPCISelLowering.cpp:  if (isFourElementShuffle) {
     758lib/Target/PowerPC/PPCISelLowering.cpp:    // Compute the index in the perfect shuffle table.
     759lib/Target/PowerPC/PPCISelLowering.cpp:    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
     760lib/Target/PowerPC/PPCISelLowering.cpp:    // used (perhaps because there are multiple permutes with the same shuffle
     761lib/Target/PowerPC/PPCISelLowering.cpp:    // As a compromise, we only emit discrete instructions if the shuffle can be
     762lib/Target/PowerPC/PPCISelLowering.cpp:      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
     763lib/Target/PowerPC/PPCISelLowering.cpp:    return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
     764lib/Target/PowerPC/PPCISelLowering.h:    /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
     765lib/Target/PowerPC/PPCISelLowering.h:    bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
     766lib/Target/PowerPC/PPCISelLowering.h:    /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
     767lib/Target/PowerPC/PPCISelLowering.h:    bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
     768lib/Target/PowerPC/PPCISelLowering.h:    /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
     769lib/Target/PowerPC/PPCISelLowering.h:    bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
     770lib/Target/PowerPC/PPCISelLowering.h:    /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
     771lib/Target/PowerPC/PPCISelLowering.h:    bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
     772lib/Target/PowerPC/PPCISelLowering.h:    /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
     773lib/Target/PowerPC/PPCISelLowering.h:    int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
     774lib/Target/PowerPC/PPCISelLowering.h:    /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
     775lib/Target/PowerPC/PPCISelLowering.h:    bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
     776lib/Target/PowerPC/PPCISelLowering.h:    /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
     777lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     778lib/Target/PowerPC/PPCInstrAltivec.td:                              (vector_shuffle node:$lhs, node:$rhs), [{
     779lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
     780lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     781lib/Target/PowerPC/PPCInstrAltivec.td:                              (vector_shuffle node:$lhs, node:$rhs), [{
     782lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
     783lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     784lib/Target/PowerPC/PPCInstrAltivec.td:                                    (vector_shuffle node:$lhs, node:$rhs), [{
     785lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
     786lib/Target/PowerPC/PPCInstrAltivec.td:def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     787lib/Target/PowerPC/PPCInstrAltivec.td:                                    (vector_shuffle node:$lhs, node:$rhs), [{
     788lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
     789lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     790lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
     791lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
     792lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     793lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
     794lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
     795lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     796lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
     797lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
     798lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     799lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
     800lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
     801lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     802lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
     803lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
     804lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     805lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
     806lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
     807lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     808lib/Target/PowerPC/PPCInstrAltivec.td:                               (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
     809lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
     810lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     811lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
     812lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
     813lib/Target/PowerPC/PPCInstrAltivec.td:def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     814lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
     815lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
     816lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     817lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
     818lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
     819lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     820lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
     821lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
     822lib/Target/PowerPC/PPCInstrAltivec.td:def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     823lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
     824lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
     825lib/Target/PowerPC/PPCInstrAltivec.td:def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
     826lib/Target/PowerPC/PPCInstrAltivec.td:  return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
     827lib/Target/PowerPC/PPCInstrAltivec.td:def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     828lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
     829lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVSLDOIShuffleMask(N, false) != -1;
     830lib/Target/PowerPC/PPCInstrAltivec.td:/// vector_shuffle(X,undef,mask) by the dag combiner.
     831lib/Target/PowerPC/PPCInstrAltivec.td:def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
     832lib/Target/PowerPC/PPCInstrAltivec.td:  return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
     833lib/Target/PowerPC/PPCInstrAltivec.td:def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     834lib/Target/PowerPC/PPCInstrAltivec.td:                                   (vector_shuffle node:$lhs, node:$rhs), [{
     835lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isVSLDOIShuffleMask(N, true) != -1;
     836lib/Target/PowerPC/PPCInstrAltivec.td:// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
     837lib/Target/PowerPC/PPCInstrAltivec.td:def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
     838lib/Target/PowerPC/PPCInstrAltivec.td:def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     839lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
     840lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
     841lib/Target/PowerPC/PPCInstrAltivec.td:def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
     842lib/Target/PowerPC/PPCInstrAltivec.td:def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     843lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
     844lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
     845lib/Target/PowerPC/PPCInstrAltivec.td:def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
     846lib/Target/PowerPC/PPCInstrAltivec.td:def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
     847lib/Target/PowerPC/PPCInstrAltivec.td:                             (vector_shuffle node:$lhs, node:$rhs), [{
     848lib/Target/PowerPC/PPCInstrAltivec.td:  return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
     849lib/Target/PowerPC/PPCInstrAltivec.td:// Shuffles.
     850lib/Target/PowerPC/PPCInstrAltivec.td:                         (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
     851lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
     852lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
     853lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
     854lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
     855lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
     856lib/Target/PowerPC/PPCInstrAltivec.td:                      [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
     857lib/Target/PowerPC/PPCInstrAltivec.td:                        (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
     858lib/Target/PowerPC/PPCInstrAltivec.td:                        (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
     859lib/Target/PowerPC/PPCInstrAltivec.td:                        (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
     860lib/Target/PowerPC/PPCInstrAltivec.td:                         (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
     861lib/Target/PowerPC/PPCInstrAltivec.td:                         (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
     862lib/Target/PowerPC/PPCInstrAltivec.td:// Shuffles.
     863lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
     864lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
     865lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
     866lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
     867lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
     868lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
     869lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
     870lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
     871lib/Target/PowerPC/PPCInstrAltivec.td:def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
     872lib/Target/PowerPC/PPCPerfectShuffle.h://===-- PPCPerfectShuffle.h - Altivec Perfect Shuffle Table -----*- C++ -*-===//
     873lib/Target/PowerPC/PPCPerfectShuffle.h:// This file, which was autogenerated by llvm-PerfectShuffle, contains data
     874lib/Target/PowerPC/PPCPerfectShuffle.h:// for the optimal way to build a perfect shuffle without using vperm.
     875lib/Target/PowerPC/PPCPerfectShuffle.h:static const unsigned PerfectShuffleTable[6561+1] = {
     876lib/Target/PowerPC/PPCTargetTransformInfo.cpp:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
     877lib/Target/PowerPC/PPCTargetTransformInfo.cpp:unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
     878lib/Target/PowerPC/PPCTargetTransformInfo.cpp:  return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
     879lib/Target/PowerPC/README.txt:argument bytes for r4 and r5. The trick then would be to shuffle the argument
     880lib/Target/R600/R600TextureIntrinsicsReplacer.cpp:        Builder.CreateShuffleVector(Coord, Coord, SwizzleMask);
     881lib/Target/Sparc/SparcInstrVIS.td:def BSHUFFLE  : VISInst<0b000011100, "bshuffle">;
     882lib/Target/X86/README-FPStack.txt:The FP stackifier should handle simple permutates to reduce number of shuffle
     883lib/Target/X86/README-SSE.txt:small table + unaligned load + shuffle instead of going through memory.
     884lib/Target/X86/README-SSE.txt:  return _mm_shuffle_epi8(value,
     885lib/Target/X86/README-SSE.txt:Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}.
     886lib/Target/X86/README-SSE.txt:This can be used to simplify a variety of shuffle operations, where the
     887lib/Target/X86/README-SSE.txt:We should transform a shuffle of two vectors of constants into a single vector
     888lib/Target/X86/README-SSE.txt:doing a shuffle from v[1] to v[0] then a float store.
     889lib/Target/X86/X86FloatingPoint.cpp:    // Shuffle live registers to match the expectations of successor blocks.
     890lib/Target/X86/X86FloatingPoint.cpp:    /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
     891lib/Target/X86/X86FloatingPoint.cpp:    void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
     892lib/Target/X86/X86FloatingPoint.cpp:/// MBB. Shuffle live registers to match the expected fixed stack of any
     893lib/Target/X86/X86FloatingPoint.cpp:  // FIXME: This can probably be combined with the shuffle below.
     894lib/Target/X86/X86FloatingPoint.cpp:    shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
     895lib/Target/X86/X86FloatingPoint.cpp:/// shuffleStackTop - emit fxch instructions before I to shuffle the top
     896lib/Target/X86/X86FloatingPoint.cpp:void FPS::shuffleStackTop(const unsigned char *FixStack,
     897lib/Target/X86/X86FloatingPoint.cpp:    shuffleStackTop(PendingST, NumPendingSTs, I);
     898lib/Target/X86/X86ISelDAGToDAG.cpp:  // elements.  This is a vector shuffle from the zero vector.
     899lib/Target/X86/X86ISelLowering.cpp:#include "Utils/X86ShuffleDecode.h"
     900lib/Target/X86/X86ISelLowering.cpp:    // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
     901lib/Target/X86/X86ISelLowering.cpp:static bool isTargetShuffle(unsigned Opcode) {
     902lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
     903lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
     904lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
     905lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
     906lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
     907lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
     908lib/Target/X86/X86ISelLowering.cpp:static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
     909lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("Unknown x86 shuffle node");
     910lib/Target/X86/X86ISelLowering.cpp:/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
     911lib/Target/X86/X86ISelLowering.cpp:/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
     912lib/Target/X86/X86ISelLowering.cpp:  // Upper quadword shuffled.
     913lib/Target/X86/X86ISelLowering.cpp:    // Upper quadword shuffled.
     914lib/Target/X86/X86ISelLowering.cpp:/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
     915lib/Target/X86/X86ISelLowering.cpp:  // Lower quadword shuffled.
     916lib/Target/X86/X86ISelLowering.cpp:    // Lower quadword shuffled.
     917lib/Target/X86/X86ISelLowering.cpp:/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
     918lib/Target/X86/X86ISelLowering.cpp:  // Do not handle 64-bit element shuffles with palignr.
     919lib/Target/X86/X86ISelLowering.cpp:/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
     920lib/Target/X86/X86ISelLowering.cpp:static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
     921lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to 128/256-bit
     922lib/Target/X86/X86ISelLowering.cpp:/// reverse of what x86 shuffles want.
     923lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
     924lib/Target/X86/X86ISelLowering.cpp:/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
     925lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
     926lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVLHPS.
     927lib/Target/X86/X86ISelLowering.cpp:SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
     928lib/Target/X86/X86ISelLowering.cpp:    Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
     929lib/Target/X86/X86ISelLowering.cpp:    Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
     930lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
     931lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to UNPCKL.
     932lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to UNPCKH.
     933lib/Target/X86/X86ISelLowering.cpp:/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
     934lib/Target/X86/X86ISelLowering.cpp:/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
     935lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVSS,
     936lib/Target/X86/X86ISelLowering.cpp:/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
     937lib/Target/X86/X86ISelLowering.cpp:/// shuffle bellow:
     938lib/Target/X86/X86ISelLowering.cpp:///   vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
     939lib/Target/X86/X86ISelLowering.cpp:  // The shuffle result is divided into half A and half B. In total the two
     940lib/Target/X86/X86ISelLowering.cpp:/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
     941lib/Target/X86/X86ISelLowering.cpp:static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
     942lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
     943lib/Target/X86/X86ISelLowering.cpp:/// In VPERMILPD the two lanes could be shuffled independently of each other
     944lib/Target/X86/X86ISelLowering.cpp:/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
     945lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
     946lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
     947lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to 256-bit
     948lib/Target/X86/X86ISelLowering.cpp:/// specifies a shuffle of elements that is suitable for input to 128-bit
     949lib/Target/X86/X86ISelLowering.cpp:/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
     950lib/Target/X86/X86ISelLowering.cpp:static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
     951lib/Target/X86/X86ISelLowering.cpp:/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
     952lib/Target/X86/X86ISelLowering.cpp:static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
     953lib/Target/X86/X86ISelLowering.cpp:/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
     954lib/Target/X86/X86ISelLowering.cpp:static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
     955lib/Target/X86/X86ISelLowering.cpp:/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
     956lib/Target/X86/X86ISelLowering.cpp:static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
     957lib/Target/X86/X86ISelLowering.cpp:/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
     958lib/Target/X86/X86ISelLowering.cpp:static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
     959lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
     960lib/Target/X86/X86ISelLowering.cpp:/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
     961lib/Target/X86/X86ISelLowering.cpp:/// FIXME: move to dag combiner / method on ShuffleVectorSDNode
     962lib/Target/X86/X86ISelLowering.cpp:static bool isZeroShuffle(ShuffleVectorSDNode *N) {
     963lib/Target/X86/X86ISelLowering.cpp:/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
     964lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
     965lib/Target/X86/X86ISelLowering.cpp:/// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
     966lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
     967lib/Target/X86/X86ISelLowering.cpp:/// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
     968lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
     969lib/Target/X86/X86ISelLowering.cpp:// a generic shuffle instruction because the target has no such instructions.
     970lib/Target/X86/X86ISelLowering.cpp:// Generate shuffles which repeat i16 and i8 several times until they can be
     971lib/Target/X86/X86ISelLowering.cpp:// represented by v4f32 and then be manipulated by target suported shuffles.
     972lib/Target/X86/X86ISelLowering.cpp:/// getLegalSplat - Generate a legal splat with supported x86 shuffles
     973lib/Target/X86/X86ISelLowering.cpp:    V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
     974lib/Target/X86/X86ISelLowering.cpp:    V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
     975lib/Target/X86/X86ISelLowering.cpp:/// PromoteSplat - Splat is promoted to target supported vector shuffles.
     976lib/Target/X86/X86ISelLowering.cpp:static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
     977lib/Target/X86/X86ISelLowering.cpp:  // All i16 and i8 vector types can't be used directly by a generic shuffle
     978lib/Target/X86/X86ISelLowering.cpp:  // instruction because the target has no such instruction. Generate shuffles
     979lib/Target/X86/X86ISelLowering.cpp:  // be manipulated by target suported shuffles.
     980lib/Target/X86/X86ISelLowering.cpp:  // to use VPERM* to shuffle the vectors
     981lib/Target/X86/X86ISelLowering.cpp:/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
     982lib/Target/X86/X86ISelLowering.cpp:/// vector of zero or undef vector.  This produces a shuffle where the low
     983lib/Target/X86/X86ISelLowering.cpp:/// Idx.  This produces a shuffle mask like 4,1,2,3 (idx=0) or  0,1,2,4 (idx=3).
     984lib/Target/X86/X86ISelLowering.cpp:static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
     985lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
     986lib/Target/X86/X86ISelLowering.cpp:/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
     987lib/Target/X86/X86ISelLowering.cpp:static bool getTargetShuffleMask(SDNode *N, MVT VT,
     988lib/Target/X86/X86ISelLowering.cpp:  default: llvm_unreachable("unknown target shuffle node");
     989lib/Target/X86/X86ISelLowering.cpp:/// getShuffleScalarElt - Returns the scalar element that will make up the ith
     990lib/Target/X86/X86ISelLowering.cpp:/// element of the result of the vector shuffle.
     991lib/Target/X86/X86ISelLowering.cpp:static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
     992lib/Target/X86/X86ISelLowering.cpp:  if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
     993lib/Target/X86/X86ISelLowering.cpp:    return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
     994lib/Target/X86/X86ISelLowering.cpp:  // Recurse into target specific vector shuffles to find scalars.
     995lib/Target/X86/X86ISelLowering.cpp:  if (isTargetShuffle(Opcode)) {
     996lib/Target/X86/X86ISelLowering.cpp:    SmallVector<int, 16> ShuffleMask;
     997lib/Target/X86/X86ISelLowering.cpp:    if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
     998lib/Target/X86/X86ISelLowering.cpp:    int Elt = ShuffleMask[Index];
     999lib/Target/X86/X86ISelLowering.cpp:    return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
     1000lib/Target/X86/X86ISelLowering.cpp:/// shuffle operation which come from a consecutively from a zero. The
     1001lib/Target/X86/X86ISelLowering.cpp:static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
     1002lib/Target/X86/X86ISelLowering.cpp:    SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
     1003lib/Target/X86/X86ISelLowering.cpp:/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
     1004lib/Target/X86/X86ISelLowering.cpp:bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
     1005lib/Target/X86/X86ISelLowering.cpp:/// isVectorShiftRight - Returns true if the shuffle can be implemented as a
     1006lib/Target/X86/X86ISelLowering.cpp:static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
     1007lib/Target/X86/X86ISelLowering.cpp:  //   vector_shuffle V1, V2 <1, 2, 3, X>
     1008lib/Target/X86/X86ISelLowering.cpp:  if (!isShuffleMaskConsecutive(SVOp,
     1009lib/Target/X86/X86ISelLowering.cpp:/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
     1010lib/Target/X86/X86ISelLowering.cpp:static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
     1011lib/Target/X86/X86ISelLowering.cpp:  //   vector_shuffle V1, V2 <X, X, 4, 5>
     1012lib/Target/X86/X86ISelLowering.cpp:  if (!isShuffleMaskConsecutive(SVOp,
     1013lib/Target/X86/X86ISelLowering.cpp:/// isVectorShift - Returns true if the shuffle can be implemented as a
     1014lib/Target/X86/X86ISelLowering.cpp:static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
     1015lib/Target/X86/X86ISelLowering.cpp:  // the shuffle mask.
     1016lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
     1017lib/Target/X86/X86ISelLowering.cpp:/// 2. A splat shuffle which uses a scalar_to_vector node which comes from
     1018lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     1019lib/Target/X86/X86ISelLowering.cpp:      // Shuffles must have a splat mask where the first element is
     1020lib/Target/X86/X86ISelLowering.cpp:static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
     1021lib/Target/X86/X86ISelLowering.cpp:        // Quit if more than 2 vectors to shuffle
     1022lib/Target/X86/X86ISelLowering.cpp:  SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
     1023lib/Target/X86/X86ISelLowering.cpp:    // a constant pool load than it is to do a movd + shuffle.
     1024lib/Target/X86/X86ISelLowering.cpp:        // convert it to a vector with movd (S2V+shuffle to zero extend).
     1025lib/Target/X86/X86ISelLowering.cpp:        Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
     1026lib/Target/X86/X86ISelLowering.cpp:          Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
     1027lib/Target/X86/X86ISelLowering.cpp:    // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
     1028lib/Target/X86/X86ISelLowering.cpp:        return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
     1029lib/Target/X86/X86ISelLowering.cpp:          Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
     1030lib/Target/X86/X86ISelLowering.cpp:    // movd/movss) to move this into the low element, then shuffle it into
     1031lib/Target/X86/X86ISelLowering.cpp:      // Turn it into a shuffle of zero and zero-extended scalar to vector.
     1032lib/Target/X86/X86ISelLowering.cpp:      Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
     1033lib/Target/X86/X86ISelLowering.cpp:      return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
     1034lib/Target/X86/X86ISelLowering.cpp:  // Splat is obviously ok. Let legalizer expand it to a shuffle.
     1035lib/Target/X86/X86ISelLowering.cpp:      // Instead of a shuffle like this:
     1036lib/Target/X86/X86ISelLowering.cpp:      // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
     1037lib/Target/X86/X86ISelLowering.cpp:      // shuffle (vload ptr)), undef, <1, 1, 1, 1>
     1038lib/Target/X86/X86ISelLowering.cpp:  // shuffles to put them in place.
     1039lib/Target/X86/X86ISelLowering.cpp:      return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
     1040lib/Target/X86/X86ISelLowering.cpp:  // If element VT is == 32 bits, turn it into a number of shuffles.
     1041lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
     1042lib/Target/X86/X86ISelLowering.cpp:    // Check for a build vector from mostly shuffle plus few inserting.
     1043lib/Target/X86/X86ISelLowering.cpp:    SDValue Sh = buildFromShuffleMostly(Op, DAG);
     1044lib/Target/X86/X86ISelLowering.cpp:        // then it is safe to just drop this shuffle: V[i] is already in the
     1045lib/Target/X86/X86ISelLowering.cpp:// Try to lower a shuffle node into a simple blend instruction.
     1046lib/Target/X86/X86ISelLowering.cpp:LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
     1047lib/Target/X86/X86ISelLowering.cpp:// v8i16 shuffles - Prefer shuffles in the following order:
     1048lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     1049lib/Target/X86/X86ISelLowering.cpp:  // of the two input vectors, shuffle them into one input vector so only a
     1050lib/Target/X86/X86ISelLowering.cpp:  // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
     1051lib/Target/X86/X86ISelLowering.cpp:  // the shuffle mask.  If a quad is scored as -1, that means that it contains
     1052lib/Target/X86/X86ISelLowering.cpp:    NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
     1053lib/Target/X86/X86ISelLowering.cpp:    // source words for the shuffle, to aid later transformations.
     1054lib/Target/X86/X86ISelLowering.cpp:    // pshufhw, that's as cheap as it gets.  Return the new shuffle.
     1055lib/Target/X86/X86ISelLowering.cpp:      NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
     1056lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
     1057lib/Target/X86/X86ISelLowering.cpp:      TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
     1058lib/Target/X86/X86ISelLowering.cpp:                             getShufflePSHUFLWImmediate(SVOp);
     1059lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
     1060lib/Target/X86/X86ISelLowering.cpp:    // shuffle mask element to zero out elements that come from V2 in the V1
     1061lib/Target/X86/X86ISelLowering.cpp:    // Calculate the shuffle mask for the second input, shuffle it, and
     1062lib/Target/X86/X86ISelLowering.cpp:    // OR it with the first shuffled input.
     1063lib/Target/X86/X86ISelLowering.cpp:    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
     1064lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
     1065lib/Target/X86/X86ISelLowering.cpp:      NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
     1066lib/Target/X86/X86ISelLowering.cpp:                                  getShufflePSHUFLWImmediate(SVOp), DAG);
     1067lib/Target/X86/X86ISelLowering.cpp:    NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
     1068lib/Target/X86/X86ISelLowering.cpp:      ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
     1069lib/Target/X86/X86ISelLowering.cpp:      NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
     1070lib/Target/X86/X86ISelLowering.cpp:                                  getShufflePSHUFHWImmediate(SVOp), DAG);
     1071lib/Target/X86/X86ISelLowering.cpp:// v16i8 shuffles - Prefer shuffles in the following order:
     1072lib/Target/X86/X86ISelLowering.cpp:// 3. [all]   v8i16 shuffle + N x pextrw + rotate + pinsrw
     1073lib/Target/X86/X86ISelLowering.cpp:static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
     1074lib/Target/X86/X86ISelLowering.cpp:    // Calculate the shuffle mask for the second input, shuffle it, and
     1075lib/Target/X86/X86ISelLowering.cpp:    // OR it with the first shuffled input.
     1076lib/Target/X86/X86ISelLowering.cpp:// v32i8 shuffles - Translate to VPSHUFB if possible.
     1077lib/Target/X86/X86ISelLowering.cpp:SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
     1078lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(MaskVals, 32);
     1079lib/Target/X86/X86ISelLowering.cpp:/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
     1080lib/Target/X86/X86ISelLowering.cpp:/// done when every pair / quad of shuffle mask elements point to elements in
     1081lib/Target/X86/X86ISelLowering.cpp:/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
     1082lib/Target/X86/X86ISelLowering.cpp:SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
     1083lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
     1084lib/Target/X86/X86ISelLowering.cpp:/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
     1085lib/Target/X86/X86ISelLowering.cpp:/// which could not be matched by any known target speficic shuffle
     1086lib/Target/X86/X86ISelLowering.cpp:LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
     1087lib/Target/X86/X86ISelLowering.cpp:  SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
     1088lib/Target/X86/X86ISelLowering.cpp:    // Build a shuffle mask for the output, discovering on the fly which
     1089lib/Target/X86/X86ISelLowering.cpp:    // input vectors to use as shuffle operands (recorded in InputUsed).
     1090lib/Target/X86/X86ISelLowering.cpp:    // If building a suitable shuffle vector proves too hard, then bail
     1091lib/Target/X86/X86ISelLowering.cpp:      // Find or create a shuffle vector operand to hold this input.
     1092lib/Target/X86/X86ISelLowering.cpp:        // shuffle vector.  Insert all elements into a BUILD_VECTOR instead.
     1093lib/Target/X86/X86ISelLowering.cpp:      // Add the mask index for the new shuffle vector.
     1094lib/Target/X86/X86ISelLowering.cpp:      // At least one input vector was used. Create a new shuffle vector.
     1095lib/Target/X86/X86ISelLowering.cpp:      Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
     1096lib/Target/X86/X86ISelLowering.cpp:/// 4 elements, and match them with several different shuffle types.
     1097lib/Target/X86/X86ISelLowering.cpp:LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
     1098lib/Target/X86/X86ISelLowering.cpp:    // implemented with two shuffles. First shuffle gather the elements.
     1099lib/Target/X86/X86ISelLowering.cpp:    // The second shuffle, which takes the first shuffle as both of its
     1100lib/Target/X86/X86ISelLowering.cpp:    V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
     1101lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
     1102lib/Target/X86/X86ISelLowering.cpp:      CommuteVectorShuffleMask(PermMask, 4);
     1103lib/Target/X86/X86ISelLowering.cpp:    V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
     1104lib/Target/X86/X86ISelLowering.cpp:      return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
     1105lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
     1106lib/Target/X86/X86ISelLowering.cpp:  // Break it into (shuffle shuffle_hi, shuffle_lo).
     1107lib/Target/X86/X86ISelLowering.cpp:  SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
     1108lib/Target/X86/X86ISelLowering.cpp:  SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
     1109lib/Target/X86/X86ISelLowering.cpp:  return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
     1110lib/Target/X86/X86ISelLowering.cpp:                     getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
     1111lib/Target/X86/X86ISelLowering.cpp:  assert(VT != MVT::v2i64 && "unsupported shuffle type");
     1112lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
     1113lib/Target/X86/X86ISelLowering.cpp:                     getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
     1114lib/Target/X86/X86ISelLowering.cpp:         "unsupported shuffle type");
     1115lib/Target/X86/X86ISelLowering.cpp:  return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
     1116lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     1117lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
     1118lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
     1119lib/Target/X86/X86ISelLowering.cpp:  // this is horrible, but will stay like this until we move all shuffle
     1120lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
     1121lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
     1122lib/Target/X86/X86ISelLowering.cpp:  assert(VT != MVT::v4i32 && "unsupported shuffle type");
     1123lib/Target/X86/X86ISelLowering.cpp:  return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
     1124lib/Target/X86/X86ISelLowering.cpp:                              getShuffleSHUFImmediate(SVOp), DAG);
     1125lib/Target/X86/X86ISelLowering.cpp:// Reduce a vector shuffle to zext.
     1126lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     1127lib/Target/X86/X86ISelLowering.cpp:  // Check the shuffle mask.
     1128lib/Target/X86/X86ISelLowering.cpp:  // Simplify the operand as it's prepared to be fed into shuffle.
     1129lib/Target/X86/X86ISelLowering.cpp:NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
     1130lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     1131lib/Target/X86/X86ISelLowering.cpp:  if (isZeroShuffle(SVOp))
     1132lib/Target/X86/X86ISelLowering.cpp:  // Check integer expanding shuffles.
     1133lib/Target/X86/X86ISelLowering.cpp:  // If the shuffle can be profitably rewritten as a narrower shuffle, then
     1134lib/Target/X86/X86ISelLowering.cpp:    SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
     1135lib/Target/X86/X86ISelLowering.cpp:      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
     1136lib/Target/X86/X86ISelLowering.cpp:        if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
     1137lib/Target/X86/X86ISelLowering.cpp:      SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
     1138lib/Target/X86/X86ISelLowering.cpp:        if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
     1139lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
     1140lib/Target/X86/X86ISelLowering.cpp:  assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
     1141lib/Target/X86/X86ISelLowering.cpp:  // When we create a shuffle node we put the UNDEF node to second operand,
     1142lib/Target/X86/X86ISelLowering.cpp:    return CommuteVectorShuffle(SVOp, DAG);
     1143lib/Target/X86/X86ISelLowering.cpp:  // Vector shuffle lowering takes 3 steps:
     1144lib/Target/X86/X86ISelLowering.cpp:  // 2) Matching of shuffles with known shuffle masks to x86 target specific
     1145lib/Target/X86/X86ISelLowering.cpp:  //    shuffle nodes.
     1146lib/Target/X86/X86ISelLowering.cpp:  // 3) Rewriting of unmatched masks into new generic shuffle operations,
     1147lib/Target/X86/X86ISelLowering.cpp:  //    so the shuffle can be broken into other shuffles and the legalizer can
     1148lib/Target/X86/X86ISelLowering.cpp:  // The general idea is that no vector_shuffle operation should be left to
     1149lib/Target/X86/X86ISelLowering.cpp:  SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
     1150lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
     1151lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
     1152lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
     1153lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
     1154lib/Target/X86/X86ISelLowering.cpp:    unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
     1155lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
     1156lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
     1157lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
     1158lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
     1159lib/Target/X86/X86ISelLowering.cpp:                                getShufflePALIGNRImmediate(SVOp),
     1160lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
     1161lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
     1162lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
     1163lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
     1164lib/Target/X86/X86ISelLowering.cpp:    return CommuteVectorShuffle(SVOp, DAG);
     1165lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(M, NumElems);
     1166lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
     1167lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
     1168lib/Target/X86/X86ISelLowering.cpp:    // new vector_shuffle with the corrected mask.p
     1169lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
     1170lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
     1171lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(M, NumElems);
     1172lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
     1173lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
     1174lib/Target/X86/X86ISelLowering.cpp:  // Normalize the node to match x86 shuffle ops if needed
     1175lib/Target/X86/X86ISelLowering.cpp:    return CommuteVectorShuffle(SVOp, DAG);
     1176lib/Target/X86/X86ISelLowering.cpp:  // The checks below are all present in isShuffleMaskLegal, but they are
     1177lib/Target/X86/X86ISelLowering.cpp:  if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
     1178lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
     1179lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
     1180lib/Target/X86/X86ISelLowering.cpp:                                getShufflePSHUFHWImmediate(SVOp),
     1181lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
     1182lib/Target/X86/X86ISelLowering.cpp:                                getShufflePSHUFLWImmediate(SVOp),
     1183lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
     1184lib/Target/X86/X86ISelLowering.cpp:                                getShuffleSHUFImmediate(SVOp), DAG);
     1185lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
     1186lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
     1187lib/Target/X86/X86ISelLowering.cpp:  // Generate target specific nodes for 128 or 256-bit shuffles only
     1188lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
     1189lib/Target/X86/X86ISelLowering.cpp:      return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
     1190lib/Target/X86/X86ISelLowering.cpp:                                  getShuffleSHUFImmediate(SVOp), DAG);
     1191lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
     1192lib/Target/X86/X86ISelLowering.cpp:                                getShuffleSHUFImmediate(SVOp), DAG);
     1193lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
     1194lib/Target/X86/X86ISelLowering.cpp:                                V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
     1195lib/Target/X86/X86ISelLowering.cpp:    return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
     1196lib/Target/X86/X86ISelLowering.cpp:  // Since no target specific shuffle was selected for this generic one,
     1197lib/Target/X86/X86ISelLowering.cpp:  // lower it into other known shuffles. FIXME: this isn't true yet, but
     1198lib/Target/X86/X86ISelLowering.cpp:  // several different shuffle types.
     1199lib/Target/X86/X86ISelLowering.cpp:  // Handle general 256-bit shuffles
     1200lib/Target/X86/X86ISelLowering.cpp:    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
     1201lib/Target/X86/X86ISelLowering.cpp:    SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
     1202lib/Target/X86/X86ISelLowering.cpp:    SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
     1203lib/Target/X86/X86ISelLowering.cpp:                         DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
     1204lib/Target/X86/X86ISelLowering.cpp:  Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
     1205lib/Target/X86/X86ISelLowering.cpp:      In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
     1206lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
     1207lib/Target/X86/X86ISelLowering.cpp:      In = DAG.getVectorShuffle(MVT::v4i64, DL,  In, DAG.getUNDEF(MVT::v4i64),
     1208lib/Target/X86/X86ISelLowering.cpp:    OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
     1209lib/Target/X86/X86ISelLowering.cpp:    OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
     1210lib/Target/X86/X86ISelLowering.cpp:    SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
     1211lib/Target/X86/X86ISelLowering.cpp:  // Handle truncation of V256 to V128 using shuffles.
     1212lib/Target/X86/X86ISelLowering.cpp:  // Prepare truncation shuffle mask
     1213lib/Target/X86/X86ISelLowering.cpp:  SDValue V = DAG.getVectorShuffle(NVT, DL,
     1214lib/Target/X86/X86ISelLowering.cpp:      SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
     1215lib/Target/X86/X86ISelLowering.cpp:      SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
     1216lib/Target/X86/X86ISelLowering.cpp:      SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
     1217lib/Target/X86/X86ISelLowering.cpp:      SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
     1218lib/Target/X86/X86ISelLowering.cpp:  // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
     1219lib/Target/X86/X86ISelLowering.cpp:  SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
     1220lib/Target/X86/X86ISelLowering.cpp:  SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
     1221lib/Target/X86/X86ISelLowering.cpp:  // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
     1222lib/Target/X86/X86ISelLowering.cpp:    SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
     1223lib/Target/X86/X86ISelLowering.cpp:    SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
     1224lib/Target/X86/X86ISelLowering.cpp:    // Merge the two vectors back together with a shuffle. This expands into 2
     1225lib/Target/X86/X86ISelLowering.cpp:    // shuffles.
     1226lib/Target/X86/X86ISelLowering.cpp:    return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
     1227lib/Target/X86/X86ISelLowering.cpp:               cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
     1228lib/Target/X86/X86ISelLowering.cpp:               cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
     1229lib/Target/X86/X86ISelLowering.cpp:/// isShuffleMaskLegal - Targets can use this to indicate that they only
     1230lib/Target/X86/X86ISelLowering.cpp:X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
     1231lib/Target/X86/X86ISelLowering.cpp:          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
     1232lib/Target/X86/X86ISelLowering.cpp:/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
     1233lib/Target/X86/X86ISelLowering.cpp:static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
     1234lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
     1235lib/Target/X86/X86ISelLowering.cpp:/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
     1236lib/Target/X86/X86ISelLowering.cpp:static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
     1237lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
     1238lib/Target/X86/X86ISelLowering.cpp:/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
     1239lib/Target/X86/X86ISelLowering.cpp:static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
     1240lib/Target/X86/X86ISelLowering.cpp:  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
     1241lib/Target/X86/X86ISelLowering.cpp:    // To match the shuffle mask, the first half of the mask should
     1242lib/Target/X86/X86ISelLowering.cpp:  // Combine some shuffles into subvector extracts and inserts:
     1243lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
     1244lib/Target/X86/X86ISelLowering.cpp:  if (isShuffleHigh128VectorInsertLow(SVOp)) {
     1245lib/Target/X86/X86ISelLowering.cpp:  // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
     1246lib/Target/X86/X86ISelLowering.cpp:  if (isShuffleLow128VectorInsertHigh(SVOp)) {
     1247lib/Target/X86/X86ISelLowering.cpp:/// PerformShuffleCombine - Performs several different shuffle combines.
     1248lib/Target/X86/X86ISelLowering.cpp:static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
     1249lib/Target/X86/X86ISelLowering.cpp:  // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
     1250lib/Target/X86/X86ISelLowering.cpp:    return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
     1251lib/Target/X86/X86ISelLowering.cpp:  // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
     1252lib/Target/X86/X86ISelLowering.cpp:    Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
     1253lib/Target/X86/X86ISelLowering.cpp:/// a sequence of vector shuffle operations.
     1254lib/Target/X86/X86ISelLowering.cpp:/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
     1255lib/Target/X86/X86ISelLowering.cpp:/// specific shuffle of a load can be folded into a single element load.
     1256lib/Target/X86/X86ISelLowering.cpp:/// shuffles have been customed lowered so we need to handle those here.
     1257lib/Target/X86/X86ISelLowering.cpp:static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
     1258lib/Target/X86/X86ISelLowering.cpp:  bool HasShuffleIntoBitcast = false;
     1259lib/Target/X86/X86ISelLowering.cpp:    HasShuffleIntoBitcast = true;
     1260lib/Target/X86/X86ISelLowering.cpp:  if (!isTargetShuffle(InVec.getOpcode()))
     1261lib/Target/X86/X86ISelLowering.cpp:  SmallVector<int, 16> ShuffleMask;
     1262lib/Target/X86/X86ISelLowering.cpp:  bool UnaryShuffle;
     1263lib/Target/X86/X86ISelLowering.cpp:  if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
     1264lib/Target/X86/X86ISelLowering.cpp:                            UnaryShuffle))
     1265lib/Target/X86/X86ISelLowering.cpp:  int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
     1266lib/Target/X86/X86ISelLowering.cpp:  // If inputs to shuffle are the same for both ops, then allow 2 uses
     1267lib/Target/X86/X86ISelLowering.cpp:  if (HasShuffleIntoBitcast) {
     1268lib/Target/X86/X86ISelLowering.cpp:    // If there's a bitcast before the shuffle, check if the load type and
     1269lib/Target/X86/X86ISelLowering.cpp:  // All checks match so transform back to vector_shuffle so that DAG combiner
     1270lib/Target/X86/X86ISelLowering.cpp:  // Create shuffle node taking into account the case that its a unary shuffle
     1271lib/Target/X86/X86ISelLowering.cpp:  SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
     1272lib/Target/X86/X86ISelLowering.cpp:  Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
     1273lib/Target/X86/X86ISelLowering.cpp:                                 InVec.getOperand(0), Shuffle,
     1274lib/Target/X86/X86ISelLowering.cpp:                                 &ShuffleMask[0]);
     1275lib/Target/X86/X86ISelLowering.cpp:  Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
     1276lib/Target/X86/X86ISelLowering.cpp:  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
     1277lib/Target/X86/X86ISelLowering.cpp:/// generation and convert it from being a bunch of shuffles and extracts
     1278lib/Target/X86/X86ISelLowering.cpp:  SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
     1279lib/Target/X86/X86ISelLowering.cpp:          return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
     1280lib/Target/X86/X86ISelLowering.cpp:        return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
     1281lib/Target/X86/X86ISelLowering.cpp:          SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
     1282lib/Target/X86/X86ISelLowering.cpp:  // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
     1283lib/Target/X86/X86ISelLowering.cpp:  // emit a shuffle and a arithmetic shift.
     1284lib/Target/X86/X86ISelLowering.cpp:  // during the shuffle phase or after the shuffle.
     1285lib/Target/X86/X86ISelLowering.cpp:    // We can't shuffle using an illegal type.
     1286lib/Target/X86/X86ISelLowering.cpp:      // Otherwise we'll shuffle the small elements in the high bits of the
     1287lib/Target/X86/X86ISelLowering.cpp:      SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
     1288lib/Target/X86/X86ISelLowering.cpp:        ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
     1289lib/Target/X86/X86ISelLowering.cpp:      SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
     1290lib/Target/X86/X86ISelLowering.cpp:                                           &ShuffleVec[0]);
     1291lib/Target/X86/X86ISelLowering.cpp:    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
     1292lib/Target/X86/X86ISelLowering.cpp:      ShuffleVec[i*SizeRatio] = i;
     1293lib/Target/X86/X86ISelLowering.cpp:    SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
     1294lib/Target/X86/X86ISelLowering.cpp:                                         &ShuffleVec[0]);
     1295lib/Target/X86/X86ISelLowering.cpp:  // Optimize trunc store (of multiple scalars) to shuffle and store.
     1296lib/Target/X86/X86ISelLowering.cpp:    // Create a type on which we perform the shuffle
     1297lib/Target/X86/X86ISelLowering.cpp:    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
     1298lib/Target/X86/X86ISelLowering.cpp:      ShuffleVec[i] = i * SizeRatio;
     1299lib/Target/X86/X86ISelLowering.cpp:    // Can't shuffle using an illegal type.
     1300lib/Target/X86/X86ISelLowering.cpp:    SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
     1301lib/Target/X86/X86ISelLowering.cpp:                                         &ShuffleVec[0]);
     1302lib/Target/X86/X86ISelLowering.cpp:  // At least one of the operands should be a vector shuffle.
     1303lib/Target/X86/X86ISelLowering.cpp:  // If LHS is not a shuffle then pretend it is the shuffle
     1304lib/Target/X86/X86ISelLowering.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
     1305lib/Target/X86/X86ISelLowering.cpp:    ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
     1306lib/Target/X86/X86ISelLowering.cpp:  // Check that the shuffles are both shuffling the same vectors.
     1307lib/Target/X86/X86ISelLowering.cpp:    CommuteVectorShuffleMask(RMask, NumElts);
     1308lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal adds from adds of shuffles.
     1309lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal subs from subs of shuffles.
     1310lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal adds from adds of shuffles.
     1311lib/Target/X86/X86ISelLowering.cpp:  // Try to synthesize horizontal adds from adds of shuffles.
     1312lib/Target/X86/X86ISelLowering.cpp:  case X86ISD::SHUFP:       // Handle all target specific shuffles
     1313lib/Target/X86/X86ISelLowering.cpp:  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
     1314lib/Target/X86/X86ISelLowering.h:      /// PSHUFB - Shuffle 16 8-bit values within a vector.
     1315lib/Target/X86/X86ISelLowering.h:      // Several flavors of instructions with vector shuffle behaviors.
     1316lib/Target/X86/X86ISelLowering.h:    /// isShuffleMaskLegal - Targets can use this to indicate that they only
     1317lib/Target/X86/X86ISelLowering.h:    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
     1318lib/Target/X86/X86ISelLowering.h:    /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
     1319lib/Target/X86/X86InstrAVX512.td:  // Shuffle with VMOVSS
     1320lib/Target/X86/X86InstrAVX512.td:  // Shuffle with VMOVSD
     1321lib/Target/X86/X86InstrAVX512.td:                   EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
     1322lib/Target/X86/X86InstrAVX512.td:                   EVEX_4V, Sched<[WriteShuffle]>;
     1323lib/Target/X86/X86InstrFragmentsSIMD.td:// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
     1324lib/Target/X86/X86InstrInfo.cpp:// FIXME: Some shuffle and unpack instructions have equivalents in different
     1325lib/Target/X86/X86InstrMMX.td:let Sched = WriteShuffle in {
     1326lib/Target/X86/X86InstrMMX.td:// -- Shuffle Instructions
     1327lib/Target/X86/X86InstrMMX.td:                          IIC_MMX_PSHUF>, Sched<[WriteShuffle]>;
     1328lib/Target/X86/X86InstrMMX.td:                          IIC_MMX_PSHUF>, Sched<[WriteShuffleLd]>;
     1329lib/Target/X86/X86InstrMMX.td:                       IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;
     1330lib/Target/X86/X86InstrMMX.td:                      IIC_MMX_PINSRW>, Sched<[WriteShuffle]>;
     1331lib/Target/X86/X86InstrMMX.td:                     IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>;
     1332lib/Target/X86/X86InstrMMX.td:let SchedRW = [WriteShuffle] in {
     1333lib/Target/X86/X86InstrSSE.td:let Sched = WriteShuffle in
     1334lib/Target/X86/X86InstrSSE.td:let Sched = WriteShuffle in
     1335lib/Target/X86/X86InstrSSE.td:              IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
     1336lib/Target/X86/X86InstrSSE.td:                  [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
     1337lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVSS
     1338lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVSD
     1339lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVSS
     1340lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVSD
     1341lib/Target/X86/X86InstrSSE.td:           Sched<[WriteFShuffle]>;
     1342lib/Target/X86/X86InstrSSE.td:    SchedRW = [WriteFShuffle] in {
     1343lib/Target/X86/X86InstrSSE.td:     Sched<[WriteFShuffleLd, ReadAfterLd]>;
     1344lib/Target/X86/X86InstrSSE.td:     Sched<[WriteFShuffleLd, ReadAfterLd]>;
     1345lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVLPS
     1346lib/Target/X86/X86InstrSSE.td:  // Shuffle with VMOVLPD
     1347lib/Target/X86/X86InstrSSE.td:  // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
     1348lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVLPS
     1349lib/Target/X86/X86InstrSSE.td:  // Shuffle with MOVLPD
     1350lib/Target/X86/X86InstrSSE.td:                      VEX_4V, Sched<[WriteFShuffle]>;
     1351lib/Target/X86/X86InstrSSE.td:                      VEX_4V, Sched<[WriteFShuffle]>;
     1352lib/Target/X86/X86InstrSSE.td:                        IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
     1353lib/Target/X86/X86InstrSSE.td:                        IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
     1354lib/Target/X86/X86InstrSSE.td:// SSE 1 & 2 - Shuffle Instructions
     1355lib/Target/X86/X86InstrSSE.td:/// sse12_shuffle - sse 1 & 2 fp shuffle instructions
     1356lib/Target/X86/X86InstrSSE.td:multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
     1357lib/Target/X86/X86InstrSSE.td:            Sched<[WriteFShuffleLd, ReadAfterLd]>;
     1358lib/Target/X86/X86InstrSSE.td:              Sched<[WriteFShuffle]>;
     1359lib/Target/X86/X86InstrSSE.td:defm VSHUFPS  : sse12_shuffle<VR128, f128mem, v4f32,
     1360lib/Target/X86/X86InstrSSE.td:defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
     1361lib/Target/X86/X86InstrSSE.td:defm VSHUFPD  : sse12_shuffle<VR128, f128mem, v2f64,
     1362lib/Target/X86/X86InstrSSE.td:defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
     1363lib/Target/X86/X86InstrSSE.td:  defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
     1364lib/Target/X86/X86InstrSSE.td:  defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
     1365lib/Target/X86/X86InstrSSE.td:                           IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
     1366lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffleLd, ReadAfterLd]>;
     1367lib/Target/X86/X86InstrSSE.td:// SSE2 - Packed Integer Shuffle Instructions
     1368lib/Target/X86/X86InstrSSE.td:multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
     1369lib/Target/X86/X86InstrSSE.td:                      IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
     1370lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffleLd]>;
     1371lib/Target/X86/X86InstrSSE.td:                       IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
     1372lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteShuffleLd]>;
     1373lib/Target/X86/X86InstrSSE.td:                IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
     1374lib/Target/X86/X86InstrSSE.td:           Sched<[WriteShuffleLd, ReadAfterLd]>;
     1375lib/Target/X86/X86InstrSSE.td:defm PSHUFD  : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
     1376lib/Target/X86/X86InstrSSE.td:defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
     1377lib/Target/X86/X86InstrSSE.td:defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
     1378lib/Target/X86/X86InstrSSE.td:      IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
     1379lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffleLd, ReadAfterLd]>;
     1380lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
     1381lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffleLd, ReadAfterLd]>;
     1382lib/Target/X86/X86InstrSSE.td:       IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
     1383lib/Target/X86/X86InstrSSE.td:       Sched<[WriteShuffleLd, ReadAfterLd]>;
     1384lib/Target/X86/X86InstrSSE.td:                Sched<[WriteShuffle]>;
     1385lib/Target/X86/X86InstrSSE.td:               Sched<[WriteShuffleLd, ReadAfterLd]>;
     1386lib/Target/X86/X86InstrSSE.td:                      IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
     1387lib/Target/X86/X86InstrSSE.td:                    [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
     1388lib/Target/X86/X86InstrSSE.td:                    Sched<[WriteFShuffle]>;
     1389lib/Target/X86/X86InstrSSE.td:let Sched = WriteShuffle in
     1390lib/Target/X86/X86InstrSSE.td:      [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
     1391lib/Target/X86/X86InstrSSE.td:      [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
     1392lib/Target/X86/X86InstrSSE.td:      []>, Sched<[WriteShuffle]>;
     1393lib/Target/X86/X86InstrSSE.td:      []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
     1394lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
     1395lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
     1396lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
     1397lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
     1398lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
     1399lib/Target/X86/X86InstrSSE.td:                                        WriteShuffle>, VEX, VEX_L;
     1400lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovsxbd, WriteShuffle>,
     1401lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovsxwq, WriteShuffle>,
     1402lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovzxbd, WriteShuffle>,
     1403lib/Target/X86/X86InstrSSE.td:                                       int_x86_avx2_pmovzxwq, WriteShuffle>,
     1404lib/Target/X86/X86InstrSSE.td:                                     WriteShuffle>, VEX;
     1405lib/Target/X86/X86InstrSSE.td:                                     WriteShuffle>, VEX;
     1406lib/Target/X86/X86InstrSSE.td:                                       WriteShuffle>, VEX, VEX_L;
     1407lib/Target/X86/X86InstrSSE.td:                                       WriteShuffle>, VEX, VEX_L;
     1408lib/Target/X86/X86InstrSSE.td:                                      WriteShuffle>;
     1409lib/Target/X86/X86InstrSSE.td:                                      WriteShuffle>;
     1410lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>;
     1411lib/Target/X86/X86InstrSSE.td:      SchedRW = [WriteShuffleLd, WriteRMW] in
     1412lib/Target/X86/X86InstrSSE.td:                   []>, Sched<[WriteShuffle]>;
     1413lib/Target/X86/X86InstrSSE.td:      SchedRW = [WriteShuffleLd, WriteRMW] in
     1414lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>;
     1415lib/Target/X86/X86InstrSSE.td:  let SchedRW = [WriteShuffleLd, WriteRMW] in
     1416lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>, REX_W;
     1417lib/Target/X86/X86InstrSSE.td:  let SchedRW = [WriteShuffleLd, WriteRMW] in
     1418lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
     1419lib/Target/X86/X86InstrSSE.td:                   imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
     1420lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
     1421lib/Target/X86/X86InstrSSE.td:                          imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
     1422lib/Target/X86/X86InstrSSE.td:      Sched<[WriteShuffle]>;
     1423lib/Target/X86/X86InstrSSE.td:                          imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
     1424lib/Target/X86/X86InstrSSE.td:      Sched<[WriteFShuffle]>;
     1425lib/Target/X86/X86InstrSSE.td:      Sched<[WriteFShuffleLd, ReadAfterLd]>;
     1426lib/Target/X86/X86InstrSSE.td:                                        int_x86_avx2_packusdw, WriteShuffle>,
     1427lib/Target/X86/X86InstrSSE.td:                                      WriteFShuffleLd>, VEX_L;
     1428lib/Target/X86/X86InstrSSE.td:                                    WriteFShuffleLd>, VEX_L;
     1429lib/Target/X86/X86InstrSSE.td:                                   WriteFShuffleLd>, VEX_L;
     1430lib/Target/X86/X86InstrSSE.td:                                           WriteFShuffle>;
     1431lib/Target/X86/X86InstrSSE.td:                                      WriteFShuffle256>, VEX_L;
     1432lib/Target/X86/X86InstrSSE.td:                                      WriteFShuffle256>, VEX_L;
     1433lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
     1434lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
     1435lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
     1436lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffle]>;
     1437lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffleLd, ReadAfterLd]>;
     1438lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffle]>;
     1439lib/Target/X86/X86InstrSSE.td:             Sched<[WriteFShuffleLd]>;
     1440lib/Target/X86/X86InstrSSE.td:          Sched<[WriteFShuffle]>;
     1441lib/Target/X86/X86InstrSSE.td:          Sched<[WriteFShuffleLd, ReadAfterLd]>;
     1442lib/Target/X86/X86InstrSSE.td:                  Sched<[WriteShuffle]>, VEX;
     1443lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteShuffle256]>, VEX, VEX_L;
     1444lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteFShuffle256]>, VEX_4V, VEX_L;
     1445lib/Target/X86/X86InstrSSE.td:                   Sched<[WriteFShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
     1446lib/Target/X86/X86InstrSSE.td:                     Sched<[WriteShuffle256]>, VEX, VEX_L;
     1447lib/Target/X86/X86InstrSSE.td:                     Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX, VEX_L;
     1448lib/Target/X86/X86InstrSSE.td:                            (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
     1449lib/Target/X86/X86InstrSSE.td:          Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
     1450lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
     1451lib/Target/X86/X86InstrSSE.td:          []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
     1452lib/Target/X86/X86InstrSSE.td:          Sched<[WriteShuffle256]>, VEX, VEX_L;
     1453lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteFShuffle,  HWPort5,  1>;
     1454lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteFShuffle256,  HWPort5,  3>;
     1455lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteShuffle,  HWPort5,  1>;
     1456lib/Target/X86/X86SchedHaswell.td:defm : HWWriteResPair<WriteShuffle256,  HWPort5,  3>;
     1457lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteFShuffle,  SBPort5,  1>;
     1458lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteShuffle,  SBPort15,  1>;
     1459lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteFShuffle256, SBPort0,  1>;
     1460lib/Target/X86/X86SchedSandyBridge.td:defm : SBWriteResPair<WriteShuffle256, SBPort0,  1>;
     1461lib/Target/X86/X86Schedule.td:defm WriteFShuffle  : X86SchedWritePair; // Floating point vector shuffles.
     1462lib/Target/X86/X86Schedule.td:defm WriteShuffle  : X86SchedWritePair; // Vector shuffles.
     1463lib/Target/X86/X86Schedule.td:defm WriteFShuffle256 : X86SchedWritePair; // Fp 256-bit width vector shuffles.
     1464lib/Target/X86/X86Schedule.td:defm WriteShuffle256 : X86SchedWritePair; // 256-bit width vector shuffles.
     1465lib/Target/X86/X86ScheduleAtom.td:                      // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
     1466lib/Target/X86/X86TargetTransformInfo.cpp:  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
     1467lib/Target/X86/X86TargetTransformInfo.cpp:      // lowered into a sequence of shuffles and 2 x pmuludq.
     1468lib/Target/X86/X86TargetTransformInfo.cpp:  // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
     1469lib/Target/X86/X86TargetTransformInfo.cpp:  // 2x pmuludq, 2x shuffle.
     1470lib/Target/X86/X86TargetTransformInfo.cpp:unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
     1471lib/Target/X86/X86TargetTransformInfo.cpp:  // We only estimate the cost of reverse shuffles.
     1472lib/Target/X86/X86TargetTransformInfo.cpp:    return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
     1473lib/Transforms/InstCombine/InstCombine.h:  Instruction *visitShuffleVectorInst(ShuffleVectorInst &SVI);
     1474lib/Transforms/InstCombine/InstCombineCalls.cpp:    // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
     1475lib/Transforms/InstCombine/InstCombineCasts.cpp:/// replace it with a shuffle (and vector/vector bitcast) if possible.
     1476lib/Transforms/InstCombine/InstCombineCasts.cpp:  // Now that the element types match, get the shuffle mask and RHS of the
     1477lib/Transforms/InstCombine/InstCombineCasts.cpp:  // shuffle to use, which depends on whether we're increasing or decreasing the
     1478lib/Transforms/InstCombine/InstCombineCasts.cpp:  SmallVector<uint32_t, 16> ShuffleMask;
     1479lib/Transforms/InstCombine/InstCombineCasts.cpp:    // If we're shrinking the number of elements, just shuffle in the low
     1480lib/Transforms/InstCombine/InstCombineCasts.cpp:    // elements from the input and use undef as the second shuffle input.
     1481lib/Transforms/InstCombine/InstCombineCasts.cpp:      ShuffleMask.push_back(i);
     1482lib/Transforms/InstCombine/InstCombineCasts.cpp:    // If we're increasing the number of elements, shuffle in all of the
     1483lib/Transforms/InstCombine/InstCombineCasts.cpp:      ShuffleMask.push_back(i);
     1484lib/Transforms/InstCombine/InstCombineCasts.cpp:      ShuffleMask.push_back(SrcElts);
     1485lib/Transforms/InstCombine/InstCombineCasts.cpp:  return new ShuffleVectorInst(InVal, V2,
     1486lib/Transforms/InstCombine/InstCombineCasts.cpp:                                                       ShuffleMask));
     1487lib/Transforms/InstCombine/InstCombineCasts.cpp:      // the casts with a shuffle and (potentially) a bitcast.
     1488lib/Transforms/InstCombine/InstCombineCasts.cpp:  if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(Src)) {
     1489lib/Transforms/InstCombine/InstCombineCasts.cpp:    // Okay, we have (bitcast (shuffle ..)).  Check to see if this is
     1490lib/Transforms/InstCombine/InstCombineCasts.cpp:      // evaluating the shuffle in the casted destination's type will allow
     1491lib/Transforms/InstCombine/InstCombineCasts.cpp:        // Return a new shuffle vector.  Use the same element ID's, as we
     1492lib/Transforms/InstCombine/InstCombineCasts.cpp:        return new ShuffleVectorInst(LHS, RHS, SVI->getOperand(2));
     1493lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:  case Instruction::ShuffleVector: {
     1494lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:    ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
     1495lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:      cast<VectorType>(Shuffle->getOperand(0)->getType())->getNumElements();
     1496lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:        unsigned MaskVal = Shuffle->getMaskValue(i);
     1497lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:                 "shufflevector mask index out of range!");
     1498lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:      unsigned MaskVal = Shuffle->getMaskValue(i);
     1499lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:                                          Shuffle->getMaskValue(i)));
     1500lib/Transforms/InstCombine/InstCombineVectorOps.cpp:// ShuffleVector.
     1501lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(V)) {
     1502lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    } else if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(I)) {
     1503lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // If this is extracting an element from a shufflevector, figure out where
     1504lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// CollectSingleShuffleElements - If V is a shuffle of values that ONLY returns
     1505lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// elements from either LHS or RHS, return the shuffle mask and true.
     1506lib/Transforms/InstCombine/InstCombineVectorOps.cpp:static bool CollectSingleShuffleElements(Value *V, Value *LHS, Value *RHS,
     1507lib/Transforms/InstCombine/InstCombineVectorOps.cpp:         "Invalid CollectSingleShuffleElements");
     1508lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
     1509lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) {
     1510lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // TODO: Handle shufflevector here!
     1511lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// CollectShuffleElements - We are building a shuffle of V, using RHS as the
     1512lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// RHS of the shuffle instruction, if it is not null.  Return a shuffle mask
     1513lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// that computes V and the LHS value of the shuffle.
     1514lib/Transforms/InstCombine/InstCombineVectorOps.cpp:static Value *CollectShuffleElements(Value *V, SmallVectorImpl<Constant*> &Mask,
     1515lib/Transforms/InstCombine/InstCombineVectorOps.cpp:         "Invalid shuffle!");
     1516lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        // otherwise we'd end up with a shuffle of three inputs.
     1517lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          Value *V = CollectShuffleElements(VecOp, Mask, RHS);
     1518lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          Value *V = CollectShuffleElements(EI->getOperand(0), Mask, RHS);
     1519lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        // vectors, return the vector and the effective shuffle.
     1520lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        if (CollectSingleShuffleElements(IEI, EI->getOperand(0), RHS, Mask))
     1521lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // TODO: Handle shufflevector here!
     1522lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // indexes are constant, try to turn this into a shufflevector operation.
     1523lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // (and any insertelements it points to), into one big shuffle.
     1524lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        Value *LHS = CollectShuffleElements(&IE, Mask, RHS);
     1525lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        // We now have a shuffle of LHS, RHS, Mask.
     1526lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        return new ShuffleVectorInst(LHS, RHS, ConstantVector::get(Mask));
     1527lib/Transforms/InstCombine/InstCombineVectorOps.cpp:/// elements were shuffled in a different order.
     1528lib/Transforms/InstCombine/InstCombineVectorOps.cpp:static bool CanEvaluateShuffled(Value *V, ArrayRef<int> Mask,
     1529lib/Transforms/InstCombine/InstCombineVectorOps.cpp:        if (!CanEvaluateShuffled(I->getOperand(i), Mask, Depth-1))
     1530lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      return CanEvaluateShuffled(I->getOperand(0), Mask, Depth-1);
     1531lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    return ConstantExpr::getShuffleVector(C, UndefValue::get(C->getType()),
     1532lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // by CanEvaluateShuffled.
     1533lib/Transforms/InstCombine/InstCombineVectorOps.cpp:Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
     1534lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  SmallVector<int, 16> Mask = SVI.getShuffleMask();
     1535lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Undefined shuffle mask -> undefined value.
     1536lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Canonicalize shuffle(x    ,x,mask) -> shuffle(x, undef,mask')
     1537lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Canonicalize shuffle(undef,x,mask) -> shuffle(x, undef,mask').
     1538lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // shuffle(undef,undef,mask) -> undef.
     1539lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    // Analyze the shuffle, are the LHS or RHS and identity shuffles?
     1540lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // Is this an identity shuffle of the LHS value?
     1541lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      // Is this an identity shuffle of the RHS value?
     1542lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    // Eliminate identity shuffles.
     1543lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (isa<UndefValue>(RHS) && CanEvaluateShuffled(LHS, Mask)) {
     1544lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // If the LHS is a shufflevector itself, see if we can combine it with this
     1545lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // one without producing an unusual shuffle.
     1546lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x1=shuffle(v1,v2,mask1)
     1547lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,undef,mask)
     1548lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(v1,undef,newMask)
     1549lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x1=shuffle(v1,undef,mask1)
     1550lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,x2,mask)
     1551lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(v1,x2,newMask)
     1552lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x2=shuffle(v2,undef,mask2)
     1553lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,x2,mask)
     1554lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,v2,newMask)
     1555lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x1=shuffle(v1,undef,mask1)
     1556lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // x2=shuffle(v2,undef,mask2)
     1557lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(x1,x2,mask)
     1558lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  //  x=shuffle(v1,v2,newMask)
     1559lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // we are absolutely afraid of producing a shuffle mask not in the input
     1560lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // shuffle into two specific shuffles: it may produce worse code.  As such,
     1561lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // we only merge two shuffles if the result is either a splat or one of the
     1562lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // input shuffle masks.  In this case, merging the shuffles just removes
     1563lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  ShuffleVectorInst* LHSShuffle = dyn_cast<ShuffleVectorInst>(LHS);
     1564lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  ShuffleVectorInst* RHSShuffle = dyn_cast<ShuffleVectorInst>(RHS);
     1565lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (LHSShuffle)
     1566lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    if (!isa<UndefValue>(LHSShuffle->getOperand(1)) && !isa<UndefValue>(RHS))
     1567lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      LHSShuffle = NULL;
     1568lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle)
     1569lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    if (!isa<UndefValue>(RHSShuffle->getOperand(1)))
     1570lib/Transforms/InstCombine/InstCombineVectorOps.cpp:      RHSShuffle = NULL;
     1571lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (!LHSShuffle && !RHSShuffle)
     1572lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (LHSShuffle) {
     1573lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    LHSOp0 = LHSShuffle->getOperand(0);
     1574lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    LHSOp1 = LHSShuffle->getOperand(1);
     1575lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle) {
     1576lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    RHSOp0 = RHSShuffle->getOperand(0);
     1577lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (LHSShuffle) {
     1578lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle && RHSOp0Width == LHSWidth) {
     1579lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    LHSMask = LHSShuffle->getShuffleMask();
     1580lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  if (RHSShuffle && newRHS != RHS)
     1581lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    RHSMask = RHSShuffle->getShuffleMask();
     1582lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // Create a new mask for the new ShuffleVectorInst so that the new
     1583lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // ShuffleVectorInst is equivalent to the original one.
     1584lib/Transforms/InstCombine/InstCombineVectorOps.cpp:          assert(isa<UndefValue>(RHSShuffle->getOperand(1))
     1585lib/Transforms/InstCombine/InstCombineVectorOps.cpp:  // If the result mask is equal to one of the original shuffle masks,
     1586lib/Transforms/InstCombine/InstCombineVectorOps.cpp:    return new ShuffleVectorInst(newLHS, newRHS, ConstantVector::get(Elts));
     1587lib/Transforms/Instrumentation/DataFlowSanitizer.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &I);
     1588lib/Transforms/Instrumentation/DataFlowSanitizer.cpp:void DFSanVisitor::visitShuffleVectorInst(ShuffleVectorInst &I) {
     1589lib/Transforms/Instrumentation/MemorySanitizer.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &I) {
     1590lib/Transforms/Instrumentation/MemorySanitizer.cpp:    setShadow(&I, IRB.CreateShuffleVector(getShadow(&I, 0), getShadow(&I, 1),
     1591lib/Transforms/ObjCARC/ObjCARCUtil.cpp:    case Instruction::ShuffleVector:
     1592lib/Transforms/Scalar/EarlyCSE.cpp:             isa<InsertElementInst>(Inst) || isa<ShuffleVectorInst>(Inst) ||
     1593lib/Transforms/Scalar/EarlyCSE.cpp:          isa<ShuffleVectorInst>(Inst)) && "Invalid/unknown instruction");
     1594lib/Transforms/Scalar/GVN.cpp:    case Instruction::ShuffleVector:
     1595lib/Transforms/Scalar/LICM.cpp:      !isa<ShuffleVectorInst>(I) && !isa<ExtractValueInst>(I) &&
     1596lib/Transforms/Scalar/SCCP.cpp:  void visitShuffleVectorInst(ShuffleVectorInst &I);
     1597lib/Transforms/Scalar/SCCP.cpp:void SCCPSolver::visitShuffleVectorInst(ShuffleVectorInst &I) {
     1598lib/Transforms/Scalar/SCCP.cpp:    markConstant(&I, ConstantExpr::getShuffleVector(V1, V2, Mask));
     1599lib/Transforms/Scalar/SROA.cpp:static cl::opt<bool> SROARandomShuffleSlices("sroa-random-shuffle-slices",
     1600lib/Transforms/Scalar/SROA.cpp:  if (SROARandomShuffleSlices) {
     1601lib/Transforms/Scalar/SROA.cpp:    std::shuffle(Slices.begin(), Slices.end(), MT);
     1602lib/Transforms/Scalar/SROA.cpp:  V = IRB.CreateShuffleVector(V, UndefValue::get(V->getType()),
     1603lib/Transforms/Scalar/SROA.cpp:  DEBUG(dbgs() << "     shuffle: " << *V << "\n");
     1604lib/Transforms/Scalar/SROA.cpp:  // use a shuffle vector to widen it with undef elements, and then
     1605lib/Transforms/Scalar/SROA.cpp:  // a second shuffle vector to select between the loaded vector and the
     1606lib/Transforms/Scalar/SROA.cpp:  V = IRB.CreateShuffleVector(V, UndefValue::get(V->getType()),
     1607lib/Transforms/Scalar/SROA.cpp:  DEBUG(dbgs() << "    shuffle: " << *V << "\n");
     1608lib/Transforms/Scalar/Scalarizer.cpp:  bool visitShuffleVectorInst(ShuffleVectorInst &);
     1609lib/Transforms/Scalar/Scalarizer.cpp:bool Scalarizer::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
     1610lib/Transforms/Vectorize/BBVectorize.cpp:    void fillNewShuffleMask(LLVMContext& Context, Instruction *J,
     1611lib/Transforms/Vectorize/BBVectorize.cpp:    Value *getReplacementShuffleMask(LLVMContext& Context, Instruction *I,
     1612lib/Transforms/Vectorize/BBVectorize.cpp:      } else if (ShuffleVectorInst *SI = dyn_cast<ShuffleVectorInst>(I)) {
     1613lib/Transforms/Vectorize/BBVectorize.cpp:      case Instruction::ShuffleVector:
     1614lib/Transforms/Vectorize/BBVectorize.cpp:    } else if (!(I->isBinaryOp() || isa<ShuffleVectorInst>(I) ||
     1615lib/Transforms/Vectorize/BBVectorize.cpp:      // instructions (because combining these often results in a shuffle),
     1616lib/Transforms/Vectorize/BBVectorize.cpp:        // shuffle chains.
     1617lib/Transforms/Vectorize/BBVectorize.cpp:          if (!isa<ShuffleVectorInst>(S->first) &&
     1618lib/Transforms/Vectorize/BBVectorize.cpp:          // the cost of shuffles.
     1619lib/Transforms/Vectorize/BBVectorize.cpp:                int ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
     1620lib/Transforms/Vectorize/BBVectorize.cpp:                    ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
     1621lib/Transforms/Vectorize/BBVectorize.cpp:                    ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
     1622lib/Transforms/Vectorize/BBVectorize.cpp:          // to shuffles, inserts or extracts can be merged, and so contribute
     1623lib/Transforms/Vectorize/BBVectorize.cpp:              if (ShuffleVectorInst *SI = dyn_cast<ShuffleVectorInst>(*I)) {
     1624lib/Transforms/Vectorize/BBVectorize.cpp:                // Shuffle can be folded if it has no other input
     1625lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
     1626lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
     1627lib/Transforms/Vectorize/BBVectorize.cpp:              if (ShuffleVectorInst *SI = dyn_cast<ShuffleVectorInst>(*I)) {
     1628lib/Transforms/Vectorize/BBVectorize.cpp:                // Shuffle can be folded if it has no other input
     1629lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
     1630lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
     1631lib/Transforms/Vectorize/BBVectorize.cpp:                // type, then they can be replaced with a shuffle
     1632lib/Transforms/Vectorize/BBVectorize.cpp:                // If both are a shuffle with equal operand types and only two
     1633lib/Transforms/Vectorize/BBVectorize.cpp:                // shuffle
     1634lib/Transforms/Vectorize/BBVectorize.cpp:                ShuffleVectorInst *SIO1 = dyn_cast<ShuffleVectorInst>(O1),
     1635lib/Transforms/Vectorize/BBVectorize.cpp:                                  *SIO2 = dyn_cast<ShuffleVectorInst>(O2);
     1636lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
     1637lib/Transforms/Vectorize/BBVectorize.cpp:                  ESContrib = std::min(ESContrib, (int) TTI->getShuffleCost(
     1638lib/Transforms/Vectorize/BBVectorize.cpp:                // both need to be shuffled together.
     1639lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib += (int) getInstrCost(Instruction::ShuffleVector,
     1640lib/Transforms/Vectorize/BBVectorize.cpp:                // both need to be shuffled together.
     1641lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib += (int) getInstrCost(Instruction::ShuffleVector,
     1642lib/Transforms/Vectorize/BBVectorize.cpp:                ESContrib = (int) getInstrCost(Instruction::ShuffleVector,
     1643lib/Transforms/Vectorize/BBVectorize.cpp:                  ESContrib += (int) getInstrCost(Instruction::ShuffleVector,
     1644lib/Transforms/Vectorize/BBVectorize.cpp:  void BBVectorize::fillNewShuffleMask(LLVMContext& Context, Instruction *J,
     1645lib/Transforms/Vectorize/BBVectorize.cpp:      int m = cast<ShuffleVectorInst>(J)->getMaskValue(v);
     1646lib/Transforms/Vectorize/BBVectorize.cpp:  // Returns the value that is to be used as the vector-shuffle mask to the
     1647lib/Transforms/Vectorize/BBVectorize.cpp:  Value *BBVectorize::getReplacementShuffleMask(LLVMContext& Context,
     1648lib/Transforms/Vectorize/BBVectorize.cpp:    // This is the shuffle mask. We need to append the second
     1649lib/Transforms/Vectorize/BBVectorize.cpp:    fillNewShuffleMask(Context, I, 0,        NumInElemJ, NumInElemI,
     1650lib/Transforms/Vectorize/BBVectorize.cpp:    fillNewShuffleMask(Context, J, NumElemI, NumInElemI, NumInElemJ,
     1651lib/Transforms/Vectorize/BBVectorize.cpp:    // exist). We might need a shuffle.
     1652lib/Transforms/Vectorize/BBVectorize.cpp:    ShuffleVectorInst *LSV = dyn_cast<ShuffleVectorInst>(LOp);
     1653lib/Transforms/Vectorize/BBVectorize.cpp:    ShuffleVectorInst *HSV = dyn_cast<ShuffleVectorInst>(HOp);
     1654lib/Transforms/Vectorize/BBVectorize.cpp:    // FIXME: If we're fusing shuffle instructions, then we can't apply this
     1655lib/Transforms/Vectorize/BBVectorize.cpp:    // optimization. The input vectors to the shuffle might be a different
     1656lib/Transforms/Vectorize/BBVectorize.cpp:    // length from the shuffle outputs. Unfortunately, the replacement
     1657lib/Transforms/Vectorize/BBVectorize.cpp:    // shuffle mask has already been formed, and the mask entries are sensitive
     1658lib/Transforms/Vectorize/BBVectorize.cpp:    bool IsSizeChangeShuffle =
     1659lib/Transforms/Vectorize/BBVectorize.cpp:      isa<ShuffleVectorInst>(L) &&
     1660lib/Transforms/Vectorize/BBVectorize.cpp:    if ((LEE || LSV) && (HEE || HSV) && !IsSizeChangeShuffle) {
     1661lib/Transforms/Vectorize/BBVectorize.cpp:          // A shuffle is needed.
     1662lib/Transforms/Vectorize/BBVectorize.cpp:            new ShuffleVectorInst(I1, UndefValue::get(I1T),
     1663lib/Transforms/Vectorize/BBVectorize.cpp:        // smaller one will need to grow before they can be shuffled together.
     1664lib/Transforms/Vectorize/BBVectorize.cpp:            new ShuffleVectorInst(I1, UndefValue::get(I1T),
     1665lib/Transforms/Vectorize/BBVectorize.cpp:            new ShuffleVectorInst(I2, UndefValue::get(I2T),
     1666lib/Transforms/Vectorize/BBVectorize.cpp:        // Now that both I1 and I2 are the same length we can shuffle them
     1667lib/Transforms/Vectorize/BBVectorize.cpp:          new ShuffleVectorInst(I1, I2, ConstantVector::get(Mask),
     1668lib/Transforms/Vectorize/BBVectorize.cpp:        // The two vector inputs to the shuffle must be the same length,
     1669lib/Transforms/Vectorize/BBVectorize.cpp:          NLOp = new ShuffleVectorInst(LOp, UndefValue::get(ArgTypeL),
     1670lib/Transforms/Vectorize/BBVectorize.cpp:          NHOp = new ShuffleVectorInst(HOp, UndefValue::get(ArgTypeH),
     1671lib/Transforms/Vectorize/BBVectorize.cpp:      Instruction *BV = new ShuffleVectorInst(LOp, HOp,
     1672lib/Transforms/Vectorize/BBVectorize.cpp:      } else if (isa<ShuffleVectorInst>(I) && o == NumOperands-1) {
     1673lib/Transforms/Vectorize/BBVectorize.cpp:        ReplacedOperands[o] = getReplacementShuffleMask(Context, I, J);
     1674lib/Transforms/Vectorize/BBVectorize.cpp:  // original I and J instructions. These are generally vector shuffles
     1675lib/Transforms/Vectorize/BBVectorize.cpp:        K1 = new ShuffleVectorInst(K, UndefValue::get(VType),
     1676lib/Transforms/Vectorize/BBVectorize.cpp:        K2 = new ShuffleVectorInst(K, UndefValue::get(VType),
     1677lib/Transforms/Vectorize/BBVectorize.cpp:        // flip it if that will yield fewer shuffles. We count the number
     1678lib/Transforms/Vectorize/LoopVectorize.cpp:  /// instruction (shuffle) for loop invariant values and for the induction
     1679lib/Transforms/Vectorize/LoopVectorize.cpp:  /// Generate a shuffle sequence that will reverse the vector Vec.
     1680lib/Transforms/Vectorize/LoopVectorize.cpp:  SmallVector<Constant*, 8> ShuffleMask;
     1681lib/Transforms/Vectorize/LoopVectorize.cpp:    ShuffleMask.push_back(Builder.getInt32(VF - i - 1));
     1682lib/Transforms/Vectorize/LoopVectorize.cpp:  return Builder.CreateShuffleVector(Vec, UndefValue::get(Vec->getType()),
     1683lib/Transforms/Vectorize/LoopVectorize.cpp:                                     ConstantVector::get(ShuffleMask),
     1684lib/Transforms/Vectorize/LoopVectorize.cpp:           isa<ShuffleVectorInst>(I) || isa<GetElementPtrInst>(I);
     1685lib/Transforms/Vectorize/LoopVectorize.cpp:      // VF is a power of 2 so we can emit the reduction using log2(VF) shuffles
     1686lib/Transforms/Vectorize/LoopVectorize.cpp:      SmallVector<Constant*, 32> ShuffleMask(VF, 0);
     1687lib/Transforms/Vectorize/LoopVectorize.cpp:          ShuffleMask[j] = Builder.getInt32(i/2 + j);
     1688lib/Transforms/Vectorize/LoopVectorize.cpp:        std::fill(&ShuffleMask[i/2], ShuffleMask.end(),
     1689lib/Transforms/Vectorize/LoopVectorize.cpp:        Builder.CreateShuffleVector(TmpVec,
     1690lib/Transforms/Vectorize/LoopVectorize.cpp:                                    ConstantVector::get(ShuffleMask),
     1691lib/Transforms/Vectorize/LoopVectorize.cpp:      Cost += TTI.getShuffleCost(TargetTransformInfo::SK_Reverse,
     1692lib/Transforms/Vectorize/SLPVectorizer.cpp:      return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy, 0);
     1693lib/Transforms/Vectorize/SLPVectorizer.cpp:/// \brief Generate a shuffle mask to be used in a reduction tree.
     1694lib/Transforms/Vectorize/SLPVectorizer.cpp:static Value *createRdxShuffleMask(unsigned VecLen, unsigned NumEltsToRdx,
     1695lib/Transforms/Vectorize/SLPVectorizer.cpp:  SmallVector<Constant *, 32> ShuffleMask(
     1696lib/Transforms/Vectorize/SLPVectorizer.cpp:      ShuffleMask[i] = Builder.getInt32(2 * i + !IsLeft);
     1697lib/Transforms/Vectorize/SLPVectorizer.cpp:      ShuffleMask[i] = Builder.getInt32(NumEltsToRdx + i);
     1698lib/Transforms/Vectorize/SLPVectorizer.cpp:  return ConstantVector::get(ShuffleMask);
     1699lib/Transforms/Vectorize/SLPVectorizer.cpp:          createRdxShuffleMask(ReduxWidth, i, true, true, Builder);
     1700lib/Transforms/Vectorize/SLPVectorizer.cpp:          createRdxShuffleMask(ReduxWidth, i, true, false, Builder);
     1701lib/Transforms/Vectorize/SLPVectorizer.cpp:        Value *LeftShuf = Builder.CreateShuffleVector(
     1702lib/Transforms/Vectorize/SLPVectorizer.cpp:        Value *RightShuf = Builder.CreateShuffleVector(
     1703lib/Transforms/Vectorize/SLPVectorizer.cpp:          createRdxShuffleMask(ReduxWidth, i, false, false, Builder);
     1704lib/Transforms/Vectorize/SLPVectorizer.cpp:        Value *Shuf = Builder.CreateShuffleVector(
     1705Robs-MacBook-Pro:llvm cameron$
     1706lib/Target/X86/Utils/X86ShuffleDecode.cpp://===-- X86ShuffleDecode.cpp - X86 shuffle decode logic -------------------===//
     1707lib/Target/X86/Utils/X86ShuffleDecode.cpp:// Define several functions to decode x86 specific shuffle semantics into a
     1708lib/Target/X86/Utils/X86ShuffleDecode.cpp:#include "X86ShuffleDecode.h"
     1709lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
     1710lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(0);
     1711lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(1);
     1712lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(2);
     1713lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask.push_back(3);
     1714lib/Target/X86/Utils/X86ShuffleDecode.cpp:  ShuffleMask[CountD] = InVal;
     1715lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero;
     1716lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero;
     1717lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero;
     1718lib/Target/X86/Utils/X86ShuffleDecode.cpp:  if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero;
     1719lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask) {
     1720lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(NElts+i);
     1721lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(i);
     1722lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask) {
     1723lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(i);
     1724lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back(NElts+i);
     1725lib/Target/X86/Utils/X86ShuffleDecode.cpp:                       SmallVectorImpl<int> &ShuffleMask) {
     1726lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(Base + l);
     1727lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodePSHUFMask - This decodes the shuffle masks for pshufd, and vpermilp*.
     1728lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
     1729lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(NewImm % NumLaneElts + l);
     1730lib/Target/X86/Utils/X86ShuffleDecode.cpp:                       SmallVectorImpl<int> &ShuffleMask) {
     1731lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + i);
     1732lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + 4 + (NewImm & 3));
     1733lib/Target/X86/Utils/X86ShuffleDecode.cpp:                       SmallVectorImpl<int> &ShuffleMask) {
     1734lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + (NewImm & 3));
     1735lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(l + i);
     1736lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
     1737lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
     1738lib/Target/X86/Utils/X86ShuffleDecode.cpp:        ShuffleMask.push_back(NewImm % NumLaneElts + s + l);
     1739lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeUNPCKHMask - This decodes the shuffle masks for unpckhps/unpckhpd
     1740lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) {
     1741lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i);          // Reads from dest/src1
     1742lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i+NumElts);  // Reads from src/src2
     1743lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeUNPCKLMask - This decodes the shuffle masks for unpcklps/unpcklpd
     1744lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) {
     1745lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i);          // Reads from dest/src1
     1746lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i+NumElts);  // Reads from src/src2
     1747lib/Target/X86/Utils/X86ShuffleDecode.cpp:                          SmallVectorImpl<int> &ShuffleMask) {
     1748lib/Target/X86/Utils/X86ShuffleDecode.cpp:    return; // Not a shuffle
     1749lib/Target/X86/Utils/X86ShuffleDecode.cpp:      ShuffleMask.push_back(i);
     1750lib/Target/X86/Utils/X86ShuffleDecode.cpp:/// DecodeVPERMMask - this decodes the shuffle masks for VPERMQ/VPERMPD.
     1751lib/Target/X86/Utils/X86ShuffleDecode.cpp:void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
     1752lib/Target/X86/Utils/X86ShuffleDecode.cpp:    ShuffleMask.push_back((Imm >> (2*i)) & 3);
     1753lib/Target/X86/Utils/X86ShuffleDecode.h://===-- X86ShuffleDecode.h - X86 shuffle decode logic -----------*-C++-*---===//
     1754lib/Target/X86/Utils/X86ShuffleDecode.h:// Define several functions to decode x86 specific shuffle semantics into a
     1755lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
     1756lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
     1757lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
     1758lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
     1759lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
     1760lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
     1761lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
     1762lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
     1763lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
     1764lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeUNPCKHMask - This decodes the shuffle masks for unpckhps/unpckhpd
     1765lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
     1766lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeUNPCKLMask - This decodes the shuffle masks for unpcklps/unpcklpd
     1767lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
     1768lib/Target/X86/Utils/X86ShuffleDecode.h:                          SmallVectorImpl<int> &ShuffleMask);
     1769lib/Target/X86/Utils/X86ShuffleDecode.h:/// DecodeVPERMMask - this decodes the shuffle masks for VPERMQ/VPERMPD.
     1770lib/Target/X86/Utils/X86ShuffleDecode.h:void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
     1771
     1772}}}